From mboxrd@z Thu Jan 1 00:00:00 1970 From: laurent.pinchart@ideasonboard.com (Laurent Pinchart) Date: Wed, 30 Nov 2016 18:03:33 +0200 Subject: [PATCH v2 1/4] drm: Add support for Amlogic Meson Graphic Controller In-Reply-To: <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> References: <1480520625-13269-1-git-send-email-narmstrong@baylibre.com> <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> Message-ID: <3713265.h5djxipShb@avalon> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org Hi Neil, Thank you for the patch. I'm afraid I don't have time for a complete review, but could you please get rid of the of_machine_is_compatible() calls and match on the VPU compatible string instead ? On Wednesday 30 Nov 2016 16:43:42 Neil Armstrong wrote: > The Amlogic Meson Display controller is composed of several components : > > DMC|---------------VPU (Video Processing > Unit)----------------|------HHI------| | > vd1 _______ _____________ _________________ | | > D |-------| |----| | | | | HDMI > PLL | D | vd2 | VIU | | Video Post | | Video Encoders > |<---|-----VCLK | R |-------| |----| Processing > | | | | | | > osd2 | | | |---| Enci ----------|----|-----VDAC------| > R |-------| CSC |----| Scalers | | Encp > ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | > Encl ----------|----|---------------| > M |-------|______|----|____________| |________________| | > | > ___|__________________________________________________________|____________ > ___| > > VIU: Video Input Unit > --------------------- > > The Video Input Unit is in charge of the pixel scanout from the DDR memory. > It fetches the frames addresses, stride and parameters from the "Canvas" > memory. This part is also in charge of the CSC (Colorspace Conversion). > It can handle 2 OSD Planes and 2 Video Planes. > > VPP: Video Post Processing > -------------------------- > > The Video Post Processing is in charge of the scaling and blending of the > various planes into a single pixel stream. > There is a special "pre-blending" used by the video planes with a dedicated > scaler and a "post-blending" to merge with the OSD Planes. > The OSD planes also have a dedicated scaler for one of the OSD. > > VENC: Video Encoders > -------------------- > > The VENC is composed of the multiple pixel encoders : > - ENCI : Interlace Video encoder for CVBS and Interlace HDMI > - ENCP : Progressive Video Encoder for HDMI > - ENCL : LCD LVDS Encoder > The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock > tree and provides the scanout clock to the VPP and VIU. > The ENCI is connected to a single VDAC for Composite Output. > The ENCI and ENCP are connected to an on-chip HDMI Transceiver. > > This driver is a DRM/KMS driver using the following DRM components : > - GEM-CMA > - PRIME-CMA > - Atomic Modesetting > - FBDev-CMA > > For the following SoCs : > - GXBB Family (S905) > - GXL Family (S905X, S905D) > - GXM Family (S912) > > The current driver only supports the CVBS PAL/NTSC output modes, but the > CRTC/Planes management should support bigger modes. > But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in > a second time. > > The Device Tree bindings makes use of the endpoints video interface > definitions to connect to the optional CVBS and in the future the HDMI > Connector nodes. > > HDMI Support is planned for a next release. > > Acked-by: Daniel Vetter > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/Kconfig | 2 + > drivers/gpu/drm/Makefile | 1 + > drivers/gpu/drm/meson/Kconfig | 9 + > drivers/gpu/drm/meson/Makefile | 4 + > drivers/gpu/drm/meson/meson_canvas.c | 68 ++ > drivers/gpu/drm/meson/meson_canvas.h | 42 + > drivers/gpu/drm/meson/meson_crtc.c | 208 +++++ > drivers/gpu/drm/meson/meson_crtc.h | 32 + > drivers/gpu/drm/meson/meson_drv.c | 343 ++++++++ > drivers/gpu/drm/meson/meson_drv.h | 60 ++ > drivers/gpu/drm/meson/meson_plane.c | 230 +++++ > drivers/gpu/drm/meson/meson_plane.h | 30 + > drivers/gpu/drm/meson/meson_registers.h | 1395 ++++++++++++++++++++++++++++ > drivers/gpu/drm/meson/meson_vclk.c | 167 ++++ > drivers/gpu/drm/meson/meson_vclk.h | 34 + > drivers/gpu/drm/meson/meson_venc.c | 254 ++++++ > drivers/gpu/drm/meson/meson_venc.h | 72 ++ > drivers/gpu/drm/meson/meson_venc_cvbs.c | 293 +++++++ > drivers/gpu/drm/meson/meson_venc_cvbs.h | 41 + > drivers/gpu/drm/meson/meson_viu.c | 331 ++++++++ > drivers/gpu/drm/meson/meson_viu.h | 64 ++ > drivers/gpu/drm/meson/meson_vpp.c | 162 ++++ > drivers/gpu/drm/meson/meson_vpp.h | 35 + > 23 files changed, 3877 insertions(+) > create mode 100644 drivers/gpu/drm/meson/Kconfig > create mode 100644 drivers/gpu/drm/meson/Makefile > create mode 100644 drivers/gpu/drm/meson/meson_canvas.c > create mode 100644 drivers/gpu/drm/meson/meson_canvas.h > create mode 100644 drivers/gpu/drm/meson/meson_crtc.c > create mode 100644 drivers/gpu/drm/meson/meson_crtc.h > create mode 100644 drivers/gpu/drm/meson/meson_drv.c > create mode 100644 drivers/gpu/drm/meson/meson_drv.h > create mode 100644 drivers/gpu/drm/meson/meson_plane.c > create mode 100644 drivers/gpu/drm/meson/meson_plane.h > create mode 100644 drivers/gpu/drm/meson/meson_registers.h > create mode 100644 drivers/gpu/drm/meson/meson_vclk.c > create mode 100644 drivers/gpu/drm/meson/meson_vclk.h > create mode 100644 drivers/gpu/drm/meson/meson_venc.c > create mode 100644 drivers/gpu/drm/meson/meson_venc.h > create mode 100644 drivers/gpu/drm/meson/meson_venc_cvbs.c > create mode 100644 drivers/gpu/drm/meson/meson_venc_cvbs.h > create mode 100644 drivers/gpu/drm/meson/meson_viu.c > create mode 100644 drivers/gpu/drm/meson/meson_viu.h > create mode 100644 drivers/gpu/drm/meson/meson_vpp.c > create mode 100644 drivers/gpu/drm/meson/meson_vpp.h -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: laurent.pinchart@ideasonboard.com (Laurent Pinchart) Date: Wed, 30 Nov 2016 18:03:33 +0200 Subject: [PATCH v2 1/4] drm: Add support for Amlogic Meson Graphic Controller In-Reply-To: <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> References: <1480520625-13269-1-git-send-email-narmstrong@baylibre.com> <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> Message-ID: <3713265.h5djxipShb@avalon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Neil, Thank you for the patch. I'm afraid I don't have time for a complete review, but could you please get rid of the of_machine_is_compatible() calls and match on the VPU compatible string instead ? On Wednesday 30 Nov 2016 16:43:42 Neil Armstrong wrote: > The Amlogic Meson Display controller is composed of several components : > > DMC|---------------VPU (Video Processing > Unit)----------------|------HHI------| | > vd1 _______ _____________ _________________ | | > D |-------| |----| | | | | HDMI > PLL | D | vd2 | VIU | | Video Post | | Video Encoders > |<---|-----VCLK | R |-------| |----| Processing > | | | | | | > osd2 | | | |---| Enci ----------|----|-----VDAC------| > R |-------| CSC |----| Scalers | | Encp > ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | > Encl ----------|----|---------------| > M |-------|______|----|____________| |________________| | > | > ___|__________________________________________________________|____________ > ___| > > VIU: Video Input Unit > --------------------- > > The Video Input Unit is in charge of the pixel scanout from the DDR memory. > It fetches the frames addresses, stride and parameters from the "Canvas" > memory. This part is also in charge of the CSC (Colorspace Conversion). > It can handle 2 OSD Planes and 2 Video Planes. > > VPP: Video Post Processing > -------------------------- > > The Video Post Processing is in charge of the scaling and blending of the > various planes into a single pixel stream. > There is a special "pre-blending" used by the video planes with a dedicated > scaler and a "post-blending" to merge with the OSD Planes. > The OSD planes also have a dedicated scaler for one of the OSD. > > VENC: Video Encoders > -------------------- > > The VENC is composed of the multiple pixel encoders : > - ENCI : Interlace Video encoder for CVBS and Interlace HDMI > - ENCP : Progressive Video Encoder for HDMI > - ENCL : LCD LVDS Encoder > The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock > tree and provides the scanout clock to the VPP and VIU. > The ENCI is connected to a single VDAC for Composite Output. > The ENCI and ENCP are connected to an on-chip HDMI Transceiver. > > This driver is a DRM/KMS driver using the following DRM components : > - GEM-CMA > - PRIME-CMA > - Atomic Modesetting > - FBDev-CMA > > For the following SoCs : > - GXBB Family (S905) > - GXL Family (S905X, S905D) > - GXM Family (S912) > > The current driver only supports the CVBS PAL/NTSC output modes, but the > CRTC/Planes management should support bigger modes. > But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in > a second time. > > The Device Tree bindings makes use of the endpoints video interface > definitions to connect to the optional CVBS and in the future the HDMI > Connector nodes. > > HDMI Support is planned for a next release. > > Acked-by: Daniel Vetter > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/Kconfig | 2 + > drivers/gpu/drm/Makefile | 1 + > drivers/gpu/drm/meson/Kconfig | 9 + > drivers/gpu/drm/meson/Makefile | 4 + > drivers/gpu/drm/meson/meson_canvas.c | 68 ++ > drivers/gpu/drm/meson/meson_canvas.h | 42 + > drivers/gpu/drm/meson/meson_crtc.c | 208 +++++ > drivers/gpu/drm/meson/meson_crtc.h | 32 + > drivers/gpu/drm/meson/meson_drv.c | 343 ++++++++ > drivers/gpu/drm/meson/meson_drv.h | 60 ++ > drivers/gpu/drm/meson/meson_plane.c | 230 +++++ > drivers/gpu/drm/meson/meson_plane.h | 30 + > drivers/gpu/drm/meson/meson_registers.h | 1395 ++++++++++++++++++++++++++++ > drivers/gpu/drm/meson/meson_vclk.c | 167 ++++ > drivers/gpu/drm/meson/meson_vclk.h | 34 + > drivers/gpu/drm/meson/meson_venc.c | 254 ++++++ > drivers/gpu/drm/meson/meson_venc.h | 72 ++ > drivers/gpu/drm/meson/meson_venc_cvbs.c | 293 +++++++ > drivers/gpu/drm/meson/meson_venc_cvbs.h | 41 + > drivers/gpu/drm/meson/meson_viu.c | 331 ++++++++ > drivers/gpu/drm/meson/meson_viu.h | 64 ++ > drivers/gpu/drm/meson/meson_vpp.c | 162 ++++ > drivers/gpu/drm/meson/meson_vpp.h | 35 + > 23 files changed, 3877 insertions(+) > create mode 100644 drivers/gpu/drm/meson/Kconfig > create mode 100644 drivers/gpu/drm/meson/Makefile > create mode 100644 drivers/gpu/drm/meson/meson_canvas.c > create mode 100644 drivers/gpu/drm/meson/meson_canvas.h > create mode 100644 drivers/gpu/drm/meson/meson_crtc.c > create mode 100644 drivers/gpu/drm/meson/meson_crtc.h > create mode 100644 drivers/gpu/drm/meson/meson_drv.c > create mode 100644 drivers/gpu/drm/meson/meson_drv.h > create mode 100644 drivers/gpu/drm/meson/meson_plane.c > create mode 100644 drivers/gpu/drm/meson/meson_plane.h > create mode 100644 drivers/gpu/drm/meson/meson_registers.h > create mode 100644 drivers/gpu/drm/meson/meson_vclk.c > create mode 100644 drivers/gpu/drm/meson/meson_vclk.h > create mode 100644 drivers/gpu/drm/meson/meson_venc.c > create mode 100644 drivers/gpu/drm/meson/meson_venc.h > create mode 100644 drivers/gpu/drm/meson/meson_venc_cvbs.c > create mode 100644 drivers/gpu/drm/meson/meson_venc_cvbs.h > create mode 100644 drivers/gpu/drm/meson/meson_viu.c > create mode 100644 drivers/gpu/drm/meson/meson_viu.h > create mode 100644 drivers/gpu/drm/meson/meson_vpp.c > create mode 100644 drivers/gpu/drm/meson/meson_vpp.h -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH v2 1/4] drm: Add support for Amlogic Meson Graphic Controller Date: Wed, 30 Nov 2016 18:03:33 +0200 Message-ID: <3713265.h5djxipShb@avalon> References: <1480520625-13269-1-git-send-email-narmstrong@baylibre.com> <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from galahad.ideasonboard.com (galahad.ideasonboard.com [IPv6:2001:4b98:dc2:45:216:3eff:febb:480d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 99E3E6E30F for ; Wed, 30 Nov 2016 16:03:18 +0000 (UTC) In-Reply-To: <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Neil Armstrong Cc: Xing.Xu@amlogic.com, victor.wan@amlogic.com, khilman@baylibre.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, jerry.cao@amlogic.com, carlo@caione.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org List-Id: dri-devel@lists.freedesktop.org SGkgTmVpbCwKClRoYW5rIHlvdSBmb3IgdGhlIHBhdGNoLgoKSSdtIGFmcmFpZCBJIGRvbid0IGhh dmUgdGltZSBmb3IgYSBjb21wbGV0ZSByZXZpZXcsIGJ1dCBjb3VsZCB5b3UgcGxlYXNlIGdldCAK cmlkIG9mIHRoZSBvZl9tYWNoaW5lX2lzX2NvbXBhdGlibGUoKSBjYWxscyBhbmQgbWF0Y2ggb24g dGhlIFZQVSBjb21wYXRpYmxlIApzdHJpbmcgaW5zdGVhZCA/CgpPbiBXZWRuZXNkYXkgMzAgTm92 IDIwMTYgMTY6NDM6NDIgTmVpbCBBcm1zdHJvbmcgd3JvdGU6Cj4gVGhlIEFtbG9naWMgTWVzb24g RGlzcGxheSBjb250cm9sbGVyIGlzIGNvbXBvc2VkIG9mIHNldmVyYWwgY29tcG9uZW50cyA6Cj4g Cj4gRE1DfC0tLS0tLS0tLS0tLS0tLVZQVSAoVmlkZW8gUHJvY2Vzc2luZwo+IFVuaXQpLS0tLS0t LS0tLS0tLS0tLXwtLS0tLS1ISEktLS0tLS18IHwKPiB2ZDEgICBfX19fX19fICAgICBfX19fX19f X19fX19fICAgIF9fX19fX19fX19fX19fX19fICAgICB8ICAgICAgICAgICAgICAgfAo+IEQgIHwt LS0tLS0tfCAgICAgIHwtLS0tfCAgICAgICAgICAgIHwgICB8ICAgICAgICAgICAgICAgIHwgICAg fCAgIEhETUkKPiBQTEwgICAgfCBEICB8IHZkMiAgIHwgVklVICB8ICAgIHwgVmlkZW8gUG9zdCB8 ICAgfCBWaWRlbyBFbmNvZGVycwo+IHw8LS0tfC0tLS0tVkNMSyAgICAgIHwgUiAgfC0tLS0tLS18 ICAgICAgfC0tLS18IFByb2Nlc3NpbmcKPiB8ICAgfCAgICAgICAgICAgICAgICB8ICAgIHwgICAg ICAgICAgICAgICB8IHwKPiBvc2QyICB8ICAgICAgfCAgICB8ICAgICAgICAgICAgfC0tLXwgRW5j aSAtLS0tLS0tLS0tfC0tLS18LS0tLS1WREFDLS0tLS0tfAo+IFIgIHwtLS0tLS0tfCBDU0MgIHwt LS0tfCBTY2FsZXJzICAgIHwgICB8IEVuY3AKPiAtLS0tLS0tLS0tfC0tLS18LS0tLUhETUktVFgt LS0tfCBBICB8IG9zZDEgIHwgICAgICB8ICAgIHwgQmxlbmRlcnMgICB8ICAgfAo+IEVuY2wgLS0t LS0tLS0tLXwtLS0tfC0tLS0tLS0tLS0tLS0tLXwKPiBNICB8LS0tLS0tLXxfX19fX198LS0tLXxf X19fX19fX19fX198ICAgfF9fX19fX19fX19fX19fX198ICAgIHwgICAgICAgICAgICAKPiAgICB8 Cj4gX19ffF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX198X19fX19fX19fX19fCj4gX19ffAo+IAo+IFZJVTogVmlkZW8gSW5wdXQgVW5pdAo+ IC0tLS0tLS0tLS0tLS0tLS0tLS0tLQo+IAo+IFRoZSBWaWRlbyBJbnB1dCBVbml0IGlzIGluIGNo YXJnZSBvZiB0aGUgcGl4ZWwgc2Nhbm91dCBmcm9tIHRoZSBERFIgbWVtb3J5Lgo+IEl0IGZldGNo ZXMgdGhlIGZyYW1lcyBhZGRyZXNzZXMsIHN0cmlkZSBhbmQgcGFyYW1ldGVycyBmcm9tIHRoZSAi Q2FudmFzIgo+IG1lbW9yeS4gVGhpcyBwYXJ0IGlzIGFsc28gaW4gY2hhcmdlIG9mIHRoZSBDU0Mg KENvbG9yc3BhY2UgQ29udmVyc2lvbikuCj4gSXQgY2FuIGhhbmRsZSAyIE9TRCBQbGFuZXMgYW5k IDIgVmlkZW8gUGxhbmVzLgo+IAo+IFZQUDogVmlkZW8gUG9zdCBQcm9jZXNzaW5nCj4gLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0KPiAKPiBUaGUgVmlkZW8gUG9zdCBQcm9jZXNzaW5nIGlzIGlu IGNoYXJnZSBvZiB0aGUgc2NhbGluZyBhbmQgYmxlbmRpbmcgb2YgdGhlCj4gdmFyaW91cyBwbGFu ZXMgaW50byBhIHNpbmdsZSBwaXhlbCBzdHJlYW0uCj4gVGhlcmUgaXMgYSBzcGVjaWFsICJwcmUt YmxlbmRpbmciIHVzZWQgYnkgdGhlIHZpZGVvIHBsYW5lcyB3aXRoIGEgZGVkaWNhdGVkCj4gc2Nh bGVyIGFuZCBhICJwb3N0LWJsZW5kaW5nIiB0byBtZXJnZSB3aXRoIHRoZSBPU0QgUGxhbmVzLgo+ IFRoZSBPU0QgcGxhbmVzIGFsc28gaGF2ZSBhIGRlZGljYXRlZCBzY2FsZXIgZm9yIG9uZSBvZiB0 aGUgT1NELgo+IAo+IFZFTkM6IFZpZGVvIEVuY29kZXJzCj4gLS0tLS0tLS0tLS0tLS0tLS0tLS0K PiAKPiBUaGUgVkVOQyBpcyBjb21wb3NlZCBvZiB0aGUgbXVsdGlwbGUgcGl4ZWwgZW5jb2RlcnMg Ogo+ICAtIEVOQ0kgOiBJbnRlcmxhY2UgVmlkZW8gZW5jb2RlciBmb3IgQ1ZCUyBhbmQgSW50ZXJs YWNlIEhETUkKPiAgLSBFTkNQIDogUHJvZ3Jlc3NpdmUgVmlkZW8gRW5jb2RlciBmb3IgSERNSQo+ ICAtIEVOQ0wgOiBMQ0QgTFZEUyBFbmNvZGVyCj4gVGhlIFZFTkMgVW5pdCBnZXRzIGEgUGl4ZWwg Q2xvY2tzIChWQ0xLKSBmcm9tIGEgZGVkaWNhdGVkIEhETUkgUExMIGFuZCBjbG9jawo+IHRyZWUg YW5kIHByb3ZpZGVzIHRoZSBzY2Fub3V0IGNsb2NrIHRvIHRoZSBWUFAgYW5kIFZJVS4KPiBUaGUg RU5DSSBpcyBjb25uZWN0ZWQgdG8gYSBzaW5nbGUgVkRBQyBmb3IgQ29tcG9zaXRlIE91dHB1dC4K PiBUaGUgRU5DSSBhbmQgRU5DUCBhcmUgY29ubmVjdGVkIHRvIGFuIG9uLWNoaXAgSERNSSBUcmFu c2NlaXZlci4KPiAKPiBUaGlzIGRyaXZlciBpcyBhIERSTS9LTVMgZHJpdmVyIHVzaW5nIHRoZSBm b2xsb3dpbmcgRFJNIGNvbXBvbmVudHMgOgo+ICAtIEdFTS1DTUEKPiAgLSBQUklNRS1DTUEKPiAg LSBBdG9taWMgTW9kZXNldHRpbmcKPiAgLSBGQkRldi1DTUEKPiAKPiBGb3IgdGhlIGZvbGxvd2lu ZyBTb0NzIDoKPiAgLSBHWEJCIEZhbWlseSAoUzkwNSkKPiAgLSBHWEwgRmFtaWx5IChTOTA1WCwg UzkwNUQpCj4gIC0gR1hNIEZhbWlseSAoUzkxMikKPiAKPiBUaGUgY3VycmVudCBkcml2ZXIgb25s eSBzdXBwb3J0cyB0aGUgQ1ZCUyBQQUwvTlRTQyBvdXRwdXQgbW9kZXMsIGJ1dCB0aGUKPiBDUlRD L1BsYW5lcyBtYW5hZ2VtZW50IHNob3VsZCBzdXBwb3J0IGJpZ2dlciBtb2Rlcy4KPiBCdXQgQWR2 YW5jZWQgQ29sb3JzcGFjZSBDb252ZXJzaW9uLCBTY2FsaW5nIGFuZCBIRE1JIE1vZGVzIHdpbGwg YmUgYWRkZWQgaW4KPiBhIHNlY29uZCB0aW1lLgo+IAo+IFRoZSBEZXZpY2UgVHJlZSBiaW5kaW5n cyBtYWtlcyB1c2Ugb2YgdGhlIGVuZHBvaW50cyB2aWRlbyBpbnRlcmZhY2UKPiBkZWZpbml0aW9u cyB0byBjb25uZWN0IHRvIHRoZSBvcHRpb25hbCBDVkJTIGFuZCBpbiB0aGUgZnV0dXJlIHRoZSBI RE1JCj4gQ29ubmVjdG9yIG5vZGVzLgo+IAo+IEhETUkgU3VwcG9ydCBpcyBwbGFubmVkIGZvciBh IG5leHQgcmVsZWFzZS4KPiAKPiBBY2tlZC1ieTogRGFuaWVsIFZldHRlciA8ZGFuaWVsLnZldHRl ckBmZndsbC5jaD4KPiBTaWduZWQtb2ZmLWJ5OiBOZWlsIEFybXN0cm9uZyA8bmFybXN0cm9uZ0Bi YXlsaWJyZS5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9LY29uZmlnICAgICAgICAgICAg ICAgICB8ICAgIDIgKwo+ICBkcml2ZXJzL2dwdS9kcm0vTWFrZWZpbGUgICAgICAgICAgICAgICAg fCAgICAxICsKPiAgZHJpdmVycy9ncHUvZHJtL21lc29uL0tjb25maWcgICAgICAgICAgIHwgICAg OSArCj4gIGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9NYWtlZmlsZSAgICAgICAgICB8ICAgIDQgKwo+ ICBkcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fY2FudmFzLmMgICAgfCAgIDY4ICsrCj4gIGRy aXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl9jYW52YXMuaCAgICB8ICAgNDIgKwo+ICBkcml2ZXJz L2dwdS9kcm0vbWVzb24vbWVzb25fY3J0Yy5jICAgICAgfCAgMjA4ICsrKysrCj4gIGRyaXZlcnMv Z3B1L2RybS9tZXNvbi9tZXNvbl9jcnRjLmggICAgICB8ICAgMzIgKwo+ICBkcml2ZXJzL2dwdS9k cm0vbWVzb24vbWVzb25fZHJ2LmMgICAgICAgfCAgMzQzICsrKysrKysrCj4gIGRyaXZlcnMvZ3B1 L2RybS9tZXNvbi9tZXNvbl9kcnYuaCAgICAgICB8ICAgNjAgKysKPiAgZHJpdmVycy9ncHUvZHJt L21lc29uL21lc29uX3BsYW5lLmMgICAgIHwgIDIzMCArKysrKwo+ICBkcml2ZXJzL2dwdS9kcm0v bWVzb24vbWVzb25fcGxhbmUuaCAgICAgfCAgIDMwICsKPiAgZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX3JlZ2lzdGVycy5oIHwgMTM5NSArKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4g IGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNvbl92Y2xrLmMgICAgICB8ICAxNjcgKysrKwo+ICBk cml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25fdmNsay5oICAgICAgfCAgIDM0ICsKPiAgZHJpdmVy cy9ncHUvZHJtL21lc29uL21lc29uX3ZlbmMuYyAgICAgIHwgIDI1NCArKysrKysKPiAgZHJpdmVy cy9ncHUvZHJtL21lc29uL21lc29uX3ZlbmMuaCAgICAgIHwgICA3MiArKwo+ICBkcml2ZXJzL2dw dS9kcm0vbWVzb24vbWVzb25fdmVuY19jdmJzLmMgfCAgMjkzICsrKysrKysKPiAgZHJpdmVycy9n cHUvZHJtL21lc29uL21lc29uX3ZlbmNfY3Zicy5oIHwgICA0MSArCj4gIGRyaXZlcnMvZ3B1L2Ry bS9tZXNvbi9tZXNvbl92aXUuYyAgICAgICB8ICAzMzEgKysrKysrKysKPiAgZHJpdmVycy9ncHUv ZHJtL21lc29uL21lc29uX3ZpdS5oICAgICAgIHwgICA2NCArKwo+ICBkcml2ZXJzL2dwdS9kcm0v bWVzb24vbWVzb25fdnBwLmMgICAgICAgfCAgMTYyICsrKysKPiAgZHJpdmVycy9ncHUvZHJtL21l c29uL21lc29uX3ZwcC5oICAgICAgIHwgICAzNSArCj4gIDIzIGZpbGVzIGNoYW5nZWQsIDM4Nzcg aW5zZXJ0aW9ucygrKQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29u L0tjb25maWcKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9NYWtl ZmlsZQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29uX2Nh bnZhcy5jCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25f Y2FudmFzLmgKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNv bl9jcnRjLmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNv bl9jcnRjLmgKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNv bl9kcnYuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29u X2Rydi5oCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vbWVzb24vbWVzb25f cGxhbmUuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29uL21lc29u X3BsYW5lLmgKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9tZXNvbi9tZXNv bl9yZWdpc3RlcnMuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX3ZjbGsuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX3ZjbGsuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX3ZlbmMuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX3ZlbmMuaAo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL21lc29u L21lc29uX3ZlbmNfY3Zicy5jCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0v bWVzb24vbWVzb25fdmVuY19jdmJzLmgKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1 L2RybS9tZXNvbi9tZXNvbl92aXUuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUv ZHJtL21lc29uL21lc29uX3ZpdS5oCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9k cm0vbWVzb24vbWVzb25fdnBwLmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2Ry bS9tZXNvbi9tZXNvbl92cHAuaAoKLS0gClJlZ2FyZHMsCgpMYXVyZW50IFBpbmNoYXJ0CgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFp bGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757415AbcK3QD0 (ORCPT ); Wed, 30 Nov 2016 11:03:26 -0500 Received: from galahad.ideasonboard.com ([185.26.127.97]:37408 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757215AbcK3QDS (ORCPT ); Wed, 30 Nov 2016 11:03:18 -0500 From: Laurent Pinchart To: Neil Armstrong Cc: airlied@linux.ie, khilman@baylibre.com, carlo@caione.org, dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, victor.wan@amlogic.com, jerry.cao@amlogic.com, Xing.Xu@amlogic.com, daniel@ffwll.ch Subject: Re: [PATCH v2 1/4] drm: Add support for Amlogic Meson Graphic Controller Date: Wed, 30 Nov 2016 18:03:33 +0200 Message-ID: <3713265.h5djxipShb@avalon> User-Agent: KMail/4.14.10 (Linux/4.8.6-gentoo; KDE/4.14.24; x86_64; ; ) In-Reply-To: <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> References: <1480520625-13269-1-git-send-email-narmstrong@baylibre.com> <1480520625-13269-2-git-send-email-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Neil, Thank you for the patch. I'm afraid I don't have time for a complete review, but could you please get rid of the of_machine_is_compatible() calls and match on the VPU compatible string instead ? On Wednesday 30 Nov 2016 16:43:42 Neil Armstrong wrote: > The Amlogic Meson Display controller is composed of several components : > > DMC|---------------VPU (Video Processing > Unit)----------------|------HHI------| | > vd1 _______ _____________ _________________ | | > D |-------| |----| | | | | HDMI > PLL | D | vd2 | VIU | | Video Post | | Video Encoders > |<---|-----VCLK | R |-------| |----| Processing > | | | | | | > osd2 | | | |---| Enci ----------|----|-----VDAC------| > R |-------| CSC |----| Scalers | | Encp > ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | > Encl ----------|----|---------------| > M |-------|______|----|____________| |________________| | > | > ___|__________________________________________________________|____________ > ___| > > VIU: Video Input Unit > --------------------- > > The Video Input Unit is in charge of the pixel scanout from the DDR memory. > It fetches the frames addresses, stride and parameters from the "Canvas" > memory. This part is also in charge of the CSC (Colorspace Conversion). > It can handle 2 OSD Planes and 2 Video Planes. > > VPP: Video Post Processing > -------------------------- > > The Video Post Processing is in charge of the scaling and blending of the > various planes into a single pixel stream. > There is a special "pre-blending" used by the video planes with a dedicated > scaler and a "post-blending" to merge with the OSD Planes. > The OSD planes also have a dedicated scaler for one of the OSD. > > VENC: Video Encoders > -------------------- > > The VENC is composed of the multiple pixel encoders : > - ENCI : Interlace Video encoder for CVBS and Interlace HDMI > - ENCP : Progressive Video Encoder for HDMI > - ENCL : LCD LVDS Encoder > The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock > tree and provides the scanout clock to the VPP and VIU. > The ENCI is connected to a single VDAC for Composite Output. > The ENCI and ENCP are connected to an on-chip HDMI Transceiver. > > This driver is a DRM/KMS driver using the following DRM components : > - GEM-CMA > - PRIME-CMA > - Atomic Modesetting > - FBDev-CMA > > For the following SoCs : > - GXBB Family (S905) > - GXL Family (S905X, S905D) > - GXM Family (S912) > > The current driver only supports the CVBS PAL/NTSC output modes, but the > CRTC/Planes management should support bigger modes. > But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in > a second time. > > The Device Tree bindings makes use of the endpoints video interface > definitions to connect to the optional CVBS and in the future the HDMI > Connector nodes. > > HDMI Support is planned for a next release. > > Acked-by: Daniel Vetter > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/Kconfig | 2 + > drivers/gpu/drm/Makefile | 1 + > drivers/gpu/drm/meson/Kconfig | 9 + > drivers/gpu/drm/meson/Makefile | 4 + > drivers/gpu/drm/meson/meson_canvas.c | 68 ++ > drivers/gpu/drm/meson/meson_canvas.h | 42 + > drivers/gpu/drm/meson/meson_crtc.c | 208 +++++ > drivers/gpu/drm/meson/meson_crtc.h | 32 + > drivers/gpu/drm/meson/meson_drv.c | 343 ++++++++ > drivers/gpu/drm/meson/meson_drv.h | 60 ++ > drivers/gpu/drm/meson/meson_plane.c | 230 +++++ > drivers/gpu/drm/meson/meson_plane.h | 30 + > drivers/gpu/drm/meson/meson_registers.h | 1395 ++++++++++++++++++++++++++++ > drivers/gpu/drm/meson/meson_vclk.c | 167 ++++ > drivers/gpu/drm/meson/meson_vclk.h | 34 + > drivers/gpu/drm/meson/meson_venc.c | 254 ++++++ > drivers/gpu/drm/meson/meson_venc.h | 72 ++ > drivers/gpu/drm/meson/meson_venc_cvbs.c | 293 +++++++ > drivers/gpu/drm/meson/meson_venc_cvbs.h | 41 + > drivers/gpu/drm/meson/meson_viu.c | 331 ++++++++ > drivers/gpu/drm/meson/meson_viu.h | 64 ++ > drivers/gpu/drm/meson/meson_vpp.c | 162 ++++ > drivers/gpu/drm/meson/meson_vpp.h | 35 + > 23 files changed, 3877 insertions(+) > create mode 100644 drivers/gpu/drm/meson/Kconfig > create mode 100644 drivers/gpu/drm/meson/Makefile > create mode 100644 drivers/gpu/drm/meson/meson_canvas.c > create mode 100644 drivers/gpu/drm/meson/meson_canvas.h > create mode 100644 drivers/gpu/drm/meson/meson_crtc.c > create mode 100644 drivers/gpu/drm/meson/meson_crtc.h > create mode 100644 drivers/gpu/drm/meson/meson_drv.c > create mode 100644 drivers/gpu/drm/meson/meson_drv.h > create mode 100644 drivers/gpu/drm/meson/meson_plane.c > create mode 100644 drivers/gpu/drm/meson/meson_plane.h > create mode 100644 drivers/gpu/drm/meson/meson_registers.h > create mode 100644 drivers/gpu/drm/meson/meson_vclk.c > create mode 100644 drivers/gpu/drm/meson/meson_vclk.h > create mode 100644 drivers/gpu/drm/meson/meson_venc.c > create mode 100644 drivers/gpu/drm/meson/meson_venc.h > create mode 100644 drivers/gpu/drm/meson/meson_venc_cvbs.c > create mode 100644 drivers/gpu/drm/meson/meson_venc_cvbs.h > create mode 100644 drivers/gpu/drm/meson/meson_viu.c > create mode 100644 drivers/gpu/drm/meson/meson_viu.h > create mode 100644 drivers/gpu/drm/meson/meson_vpp.c > create mode 100644 drivers/gpu/drm/meson/meson_vpp.h -- Regards, Laurent Pinchart