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From: David Howells <dhowells@redhat.com>
To: Linus Torvalds <torvalds@osdl.org>
Cc: David Howells <dhowells@redhat.com>,
	Paul Mackerras <paulus@samba.org>,
	"Eric W. Biederman" <ebiederm@xmission.com>,
	akpm@osdl.org, linux-arch@vger.kernel.org,
	linux-kernel@vger.kernel.org, mingo@redhat.com, alan@redhat.com,
	linuxppc64-dev@ozlabs.org
Subject: Re: [PATCH] Document Linux's memory barriers [try #4]
Date: Wed, 15 Mar 2006 01:19:02 +0000	[thread overview]
Message-ID: <3762.1142385542@warthog.cambridge.redhat.com> (raw)
In-Reply-To: <Pine.LNX.4.64.0603141609520.3618@g5.osdl.org>

Linus Torvalds <torvalds@osdl.org> wrote:

> That's not that different from doing
> 
> 	ptr = read a
> 	data = read [ptr]
> 
>   and speculating the result of the first read.

But that would lead to the situation I suggested (q == &b and d == a), not the
one Paul suggested (q == &b and d == old b) because we'd speculate on the old
value of the pointer, and so see it before it's updated, and thus still
pointing to a.

> The cache is fully coherent, but the coherency isn't _ordered_.
> 
> Remember: the smp_wmb() only orders on the _writer_ side. Not on the 
> reader side. The writer may send out the stuff in a particular order, but 
> the reader might see them in a different order because _it_ might queue 
> the bus events internally for its caches (in particular, it could end up 
> delaying updating a particular way in the cache because it's busy).

Ummm... So whilst smp_wmb() commits writes to the mercy of the cache coherency
system in a particular order, the updates can be passed over from one cache to
another and committed to the reader's cache in any order, and can even be
delayed:

	CPU 1		CPU 2		COMMENT
	===============	===============	=======================================
					a == 0, b == 1 and p == &a, q == &a
	b = 2;
	smp_wmb();			Make sure b is changed before p
	<post b=2>
			<queue b=2>
	p = &b;		q = p;
	<post p=&b>
			<queue p=&b>
			d = *q;
			<commit p=&b>
			<post q=p>
			<read *q>	Reads from b before b updated in cache
			<post d=*q>
			<commit b=2>

I presume the Alpha MB instruction forces cache queue completion in addition
to a partial ordering on memory accesses:

	CPU 1		CPU 2		COMMENT
	===============	===============	=======================================
					a == 0, b == 1 and p == &a, q == &a
	b = 2;
	smp_wmb();			Make sure b is changed before p
	<post b=2>
			<queue b=2>
	p = &b;		q = p;
	<post p=&b>
			<queue p=&b>
			smp_read_barrier_depends();
			<commit b=2>
			<commit p=&b>
			d = *q;
			<post q=p>
			<read *q>	Reads new value of b
			<post d=*q>


David

  reply	other threads:[~2006-03-15  1:19 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-03-09 20:29 [PATCH] Document Linux's memory barriers [try #4] David Howells
2006-03-09 23:34 ` Paul Mackerras
2006-03-09 23:45   ` Michael Buesch
2006-03-09 23:56     ` Linus Torvalds
2006-03-10  0:07       ` Michael Buesch
2006-03-10  0:48   ` Alan Cox
2006-03-10  0:54     ` Paul Mackerras
2006-03-10 15:19   ` David Howells
2006-03-11  0:01     ` Paul Mackerras
2006-03-10  5:28 ` Nick Piggin
2006-03-15 11:10   ` David Howells
2006-03-15 11:51     ` Nick Piggin
2006-03-15 13:47       ` David Howells
2006-03-15 23:21         ` Nick Piggin
2006-03-12 17:15 ` Eric W. Biederman
2006-03-14 21:26   ` David Howells
2006-03-14 21:26     ` David Howells
2006-03-14 21:48     ` Paul Mackerras
2006-03-14 21:48       ` Paul Mackerras
2006-03-14 23:59       ` David Howells
2006-03-14 23:59         ` David Howells
2006-03-15  0:20         ` Linus Torvalds
2006-03-15  1:19           ` David Howells [this message]
2006-03-15  1:47             ` Linus Torvalds
2006-03-15  1:25           ` Nick Piggin
2006-03-15  0:54         ` Paul Mackerras
2006-03-15  0:54           ` Paul Mackerras
2006-03-13 12:32 ` Sergei Organov
2006-03-14 20:31   ` David Howells
2006-03-14 21:11     ` linux-os (Dick Johnson)
2006-03-15  9:09       ` Sergei Organov
2006-03-15  9:04     ` Sergei Organov
2006-03-14 20:35   ` David Howells
2006-03-15  9:11     ` Sergei Organov
2006-03-15 14:23 ` [PATCH] Document Linux's memory barriers [try #5] David Howells
     [not found]   ` <20060315200956.4a9e2cb3.akpm@osdl.org>
2006-03-16 11:50     ` David Howells
2006-03-16 17:18       ` Linus Torvalds
2006-03-17  1:20         ` Nick Piggin
2006-03-16 23:17   ` Paul E. McKenney
2006-03-16 23:55     ` Linus Torvalds
2006-03-17  1:29       ` Paul E. McKenney
2006-03-17  5:32         ` Linus Torvalds
2006-03-17  6:23           ` Paul E. McKenney
2006-03-23 18:34     ` David Howells
2006-03-23 18:34       ` David Howells
2006-03-23 19:28       ` Linus Torvalds
2006-03-23 19:28         ` Linus Torvalds
2006-03-23 22:26       ` Paul E. McKenney
2006-03-23 22:26         ` Paul E. McKenney

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