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Fri, 13 Oct 2023 12:22:29 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: linux-riscv@lists.indradead.org, Conor Dooley Cc: conor@kernel.org, conor.dooley@microchip.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v3 5/6] riscv: dts: allwinner: convert isa detection to new properties Date: Fri, 13 Oct 2023 21:22:28 +0200 Message-ID: <3766810.kQq0lBPeGt@jernej-laptop> In-Reply-To: <20231009-moonlight-gray-92debdc89f30@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> <20231009-moonlight-gray-92debdc89f30@wendy> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231013_122232_190270_45728770 X-CRM114-Status: GOOD ( 12.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Dne ponedeljek, 09. oktober 2023 ob 11:37:49 CEST je Conor Dooley napisal(a): > Convert the D1 devicetrees to use the new properties > "riscv,isa-base" & "riscv,isa-extensions". > For compatibility with other projects, "riscv,isa" remains. > > Acked-by: Jernej Skrabec > Signed-off-by: Conor Dooley Applied, thanks! Best regards, Jernej > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 0856f18dc3cf..64c3c2e6cbe0 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -25,6 +25,9 @@ cpu0: cpu@0 { > mmu-type = "riscv,sv39"; > operating-points-v2 = <&opp_table_cpu>; > riscv,isa = "rv64imafdc"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > + "zifencei", "zihpm"; > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CB67CDB47E for ; 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Fri, 13 Oct 2023 12:22:30 -0700 (PDT) Received: from jernej-laptop.localnet ([188.159.248.16]) by smtp.gmail.com with ESMTPSA id i2-20020a5d5582000000b00323293bd023sm842831wrv.6.2023.10.13.12.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 12:22:29 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: linux-riscv@lists.indradead.org, Conor Dooley Cc: conor@kernel.org, conor.dooley@microchip.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v3 5/6] riscv: dts: allwinner: convert isa detection to new properties Date: Fri, 13 Oct 2023 21:22:28 +0200 Message-ID: <3766810.kQq0lBPeGt@jernej-laptop> In-Reply-To: <20231009-moonlight-gray-92debdc89f30@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> <20231009-moonlight-gray-92debdc89f30@wendy> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Dne ponedeljek, 09. oktober 2023 ob 11:37:49 CEST je Conor Dooley napisal(a): > Convert the D1 devicetrees to use the new properties > "riscv,isa-base" & "riscv,isa-extensions". > For compatibility with other projects, "riscv,isa" remains. > > Acked-by: Jernej Skrabec > Signed-off-by: Conor Dooley Applied, thanks! Best regards, Jernej > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 0856f18dc3cf..64c3c2e6cbe0 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -25,6 +25,9 @@ cpu0: cpu@0 { > mmu-type = "riscv,sv39"; > operating-points-v2 = <&opp_table_cpu>; > riscv,isa = "rv64imafdc"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > + "zifencei", "zihpm"; > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { >