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Sat, 31 Oct 2026 01:47:20 +0000 Message-ID: <384d2df7-b031-4b4e-954e-05e5cca83ea4@amd.com> Date: Fri, 30 Oct 2026 19:47:18 -0600 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/amd/display: Drop clock requirements on DCN32 when no displays are active To: Misha Nasledov , amd-gfx@lists.freedesktop.org Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher References: <20261019234232.33760-1-misha@nasledov.com> Content-Language: en-US From: Alex Hung In-Reply-To: <20261019234232.33760-1-misha@nasledov.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MW4PR02CA0024.namprd02.prod.outlook.com (2603:10b6:303:16d::9) To CY0PR12MB226969.namprd12.prod.outlook.com (2603:10b6:930:130::18) X-Archived-By: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY0PR12MB226969:EE_|BY5PR12MB4052:EE_ X-MS-Office365-Filtering-Correlation-Id: c16040d5-0cf6-45bd-70d2-08df36f0e6ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > amdgpu_dm builds the new dc_state as a copy of the old one. When the last > stream is removed, dml1_validate() returns early on pipe_cnt == 0 and > never reaches dcn32_calculate_dlg_params(), so bw.dcn.clk keeps the > dramclk/dcfclk/fclk requirements of the display that was just turned off. > dcn32_update_clocks() then keeps those hard minimums applied. > > On an RX 7900 XTX this leaves UCLK at 456 MHz and DCFCLK at 637 MHz with > the monitor off, and the board idles at 28.4 W. With this change they > drop to 96 MHz and 145 MHz and board power falls to 15.3 W. > > Reset the clock requirements in that case, as calculate_dlg_params() > already does when no HUBP is active and as the DML2 path does for > stream_count == 0. > > Signed-off-by: Misha Nasledov > --- > Tested on an RX 7900 XTX on v7.2.11, where the patch applies cleanly. > This version is against amd-staging-drm-next. > > I used an LLM to help trace the clock path and draft this change, and > I reviewed and tested it myself. > > DCN 2.0 and 2.1 (dcn20_validate_bandwidth_internal() and > dcn21_validate_bandwidth_fp() in dml/dcn20/dcn20_fpu.c) and DCN 3.0 > (dcn30_validate_bandwidth()) take the same pipe_cnt == 0 early exit, so > they probably keep stale clocks with all displays off as well. I've left > them alone because I only have DCN 3.2 hardware to test on. I'm happy to > send the same change for them if that's wanted. > > .../display/dc/resource/dcn32/dcn32_resource.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c > index c9eba16ef359..c22ffbe74d9b 100644 > --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c > @@ -1941,8 +1941,21 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_valid > out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); > DC_FP_END(); > > - if (pipe_cnt == 0) > + if (pipe_cnt == 0) { > + /* The context is a copy of the previous state, so without this the > + * clocks the last display needed stay applied with all displays off. > + */ > + context->bw_ctx.bw.dcn.clk.socclk_khz = 0; > + context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; > + context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; > + context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; > + context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; > + context->bw_ctx.bw.dcn.clk.fclk_khz = 0; > + context->bw_ctx.bw.dcn.clk.p_state_change_support = true; > + context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; > + context->bw_ctx.bw.dcn.clk.num_ways = 0; > goto validate_out; > + } > > if (!out) > goto validate_fail; > -- > 2.55.0