From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48277) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2qPa-0004nb-Ld for qemu-devel@nongnu.org; Tue, 17 May 2016 21:36:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2nOK-0008WM-7W for qemu-devel@nongnu.org; Tue, 17 May 2016 18:23:07 -0400 Received: from mail-qg0-x230.google.com ([2607:f8b0:400d:c04::230]:35277) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2nOK-0008Vy-2S for qemu-devel@nongnu.org; Tue, 17 May 2016 18:23:04 -0400 Received: by mail-qg0-x230.google.com with SMTP id f74so16549859qge.2 for ; Tue, 17 May 2016 15:23:04 -0700 (PDT) Sender: Richard Henderson Reply-To: Richard Henderson References: <1463196873-17737-1-git-send-email-cota@braap.org> <1463196873-17737-8-git-send-email-cota@braap.org> <573B5134.8060104@gmail.com> <66d14198-dab0-c72e-fe17-d022cff3feff@twiddle.net> <573B7793.9020109@gmail.com> <573B78A6.6030009@gmail.com> From: Richard Henderson Message-ID: <38bb759d-3238-709d-e1e9-b8961bc9e5c6@twiddle.net> Date: Tue, 17 May 2016 15:22:59 -0700 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 07/18] qemu-thread: add simple test-and-set spinlock List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov , "Emilio G. Cota" , QEMU Developers , MTTCG Devel Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Paolo Bonzini , Peter Crosthwaite On 05/17/2016 03:12 PM, Richard Henderson wrote: > On 05/17/2016 01:01 PM, Sergey Fedorov wrote: >>> Sorry, I can't see reading ARMv6 ARM that 1-byte access can't be atomic. What >>> I've found: >>> >>> B2.4.1 Normal memory attribute >>> (snip) >>> Shared Normal memory >>> >>> (snip) >>> ... Reads to Shared Normal Memory that are aligned in memory to the >>> size of the access must be atomic. > ... >> Looks like GCC has no trouble generating __atomic_store_n() for 1-byte bool... > > Not loads and stores, but other atomic ops like xchg. The native atomic > operations are all 4 bytes long. > > I suppose the compiler may well be able to synthesize sub-word atomic ops, but > it'll be 2 or 3 times the size of a word-sized atomic op, and for no good reason. Indeed, even with gcc 7 branch, struct foo { _Bool b; int i; } f; void a() { __atomic_exchange_n(&f.b, 1, __ATOMIC_ACQUIRE); __atomic_exchange_n(&f.i, 1, __ATOMIC_ACQUIRE); } void b() { __sync_lock_test_and_set(&f.b, 1); __sync_lock_test_and_set(&f.i, 1); } $ ./gcc/xgcc -B./gcc/ -O2 -S ~/z.c -march=armv6 $ cat z.s a: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 push {r4, r5, r6, lr} mov r6, #1 ldr r5, .L8 ldrb r3, [r5] @ zero_extendqisi2 .L2: mov r2, r6 sxtb r1, r3 mov r0, r5 mov r4, r3 bl __sync_val_compare_and_swap_1 uxtb r4, r4 uxtb r2, r0 cmp r2, r4 mov r3, r0 bne .L2 ldr r3, .L8+4 mov r2, #1 .L5: ldrex r1, [r3] strex r0, r2, [r3] cmp r0, #0 bne .L5 mcr p15, 0, r0, c7, c10, 5 pop {r4, r5, r6, pc} ... b: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 push {r4, lr} mov r1, #1 ldr r4, .L13 mov r0, r4 bl __sync_lock_test_and_set_1 add r4, r4, #4 mov r3, #1 .L11: ldrex r2, [r4] strex r1, r3, [r4] cmp r1, #0 bne .L11 mcr p15, 0, r0, c7, c10, 5 pop {r4, pc} r~