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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fb72fb71esm18717552f8f.1.2025.09.29.08.33.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Sep 2025 08:33:55 -0700 (PDT) Message-ID: <39446b6c-d7dd-4aeb-a2ee-96db03997e4a@redhat.com> Date: Mon, 29 Sep 2025 17:33:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 12/14] hw/arm/smmuv3: Use iommu_index to represent the security context To: Tao Tang , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh References: <20250925162618.191242-1-tangtao1634@phytium.com.cn> <20250926030831.1067440-1-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: <20250926030831.1067440-1-tangtao1634@phytium.com.cn> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: MMMeyHUPK0QsKGl-hUzfcNzH_Sk-5cd63AfctIWWE5Q_1759160036 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 9/26/25 5:08 AM, Tao Tang wrote: > Resending patches 12–14/14 that were missing due to a send issue. Sorry > for the noise. > > The Arm SMMUv3 architecture uses a SEC_SID (Secure StreamID) to select > the programming interface. To support future extensions like RME, which > defines four security states (Non-secure, Secure, Realm, and Root), the > QEMU model must cleanly separate these contexts for all operations. > > This commit leverages the generic iommu_index to represent this > security context. The core IOMMU layer now uses the SMMU's .attrs_to_index > callback to map a transaction's ARMSecuritySpace attribute to the > corresponding iommu_index. > > This index is then passed down to smmuv3_translate and used throughout > the model to select the correct register bank and processing logic. This > makes the iommu_index the clear QEMU equivalent of the architectural > SEC_SID, cleanly separating the contexts for all subsequent lookups. > > Signed-off-by: Tao Tang > --- > hw/arm/smmuv3.c | 37 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 36 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index eec36d5fd2..c92cc0f06a 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -1099,6 +1099,38 @@ static void smmuv3_fixup_event(SMMUEventInfo *event, hwaddr iova) > } > } > > +static SMMUSecurityIndex smmuv3_attrs_to_security_index(MemTxAttrs attrs) > +{ > + switch (attrs.space) { > + case ARMSS_Secure: > + return SMMU_SEC_IDX_S; > + case ARMSS_NonSecure: > + default: > + return SMMU_SEC_IDX_NS; > + } > +} > + > +/* > + * ARM SMMU IOMMU index mapping (implements SEC_SID from ARM SMMU): > + * iommu_idx = 0: Non-secure transactions > + * iommu_idx = 1: Secure transactions > + * > + * The iommu_idx parameter effectively implements the SEC_SID > + * (Security Stream ID) attribute from the ARM SMMU architecture > + * specification, which allows the SMMU to differentiate between > + * secure and non-secure transactions at the hardware level. > + */ > +static int smmuv3_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs) > +{ > + return smmuv3_attrs_to_security_index(attrs); > +} > + > +static int smmuv3_num_indexes(IOMMUMemoryRegion *iommu) > +{ > + /* Support 2 IOMMU indexes for now: NS/S */ > + return SMMU_SEC_IDX_NUM; > +} > + > /* Entry point to SMMU, does everything. */ > static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > IOMMUAccessFlags flag, int iommu_idx) > @@ -1111,7 +1143,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > .inval_ste_allowed = false}; > SMMUTranslationStatus status; > SMMUTransCfg *cfg = NULL; > - SMMUSecurityIndex sec_idx = SMMU_SEC_IDX_NS; > + SMMUSecurityIndex sec_idx = iommu_idx; > IOMMUTLBEntry entry = { > .target_as = &address_space_memory, > .iova = addr, > @@ -1155,6 +1187,7 @@ epilogue: > entry.perm = cached_entry->entry.perm; > entry.translated_addr = CACHED_ENTRY_TO_ADDR(cached_entry, addr); > entry.addr_mask = cached_entry->entry.addr_mask; > + entry.target_as = cached_entry->entry.target_as; this change looks unrelated to the commit desc. Eric > trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, > entry.translated_addr, entry.perm, > cfg->stage); > @@ -2534,6 +2567,8 @@ static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, > > imrc->translate = smmuv3_translate; > imrc->notify_flag_changed = smmuv3_notify_flag_changed; > + imrc->attrs_to_index = smmuv3_attrs_to_index; > + imrc->num_indexes = smmuv3_num_indexes; > } > > static const TypeInfo smmuv3_type_info = { > -- > 2.34.1 >