From mboxrd@z Thu Jan  1 00:00:00 1970
Message-ID: <39D816D8.35ED965E@mvista.com>
Date: Mon, 02 Oct 2000 01:02:16 -0400
From: Dan Malek <dan@mvista.com>
MIME-Version: 1.0
To: "Dan A. Dickey" <ddickey@charter.net>
CC: "linuxppc-embedded@lists.linuxppc.org"
 <linuxppc-embedded@lists.linuxppc.org>
Subject: Re: ethernet on fads850sar board?
References: <39D7F8FB.9C508CF1@charter.net>
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"Dan A. Dickey" wrote:

> Any ideas?

Make sure the GP I/O pins are configured properly to be SCC2 Ethernet
control/status lines.  Make sure the BCSR bits enable and properly
configure the PHY (half/full duplex, loopback, etc.).

> (And why do the baud rate generators that feed the ethernet
>  clocks need to run at 2Mhz?)

Ummm, no.....The PHY provides the clocks, they are inputs to port.
I don't know why an external clock would be set to that value.

	-- Dan

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