From: Frank Rowand <frank_rowand@mvista.com>
To: Gabriel Paubert <paubert@iram.es>
Cc: Dan Malek <dan@mvista.com>,
minyard@acm.org, linuxppc-dev@lists.linuxppc.org
Subject: Re: Allowing signal handlers to modify SE and BE
Date: Mon, 23 Oct 2000 11:11:45 -0700 [thread overview]
Message-ID: <39F47F61.EFBFFCD2@mvista.com> (raw)
In-Reply-To: Pine.HPX.4.10.10010171019190.18996-100000@gra-ux1.iram.es
Gabriel Paubert wrote:
>
> On Tue, 17 Oct 2000, Dan Malek wrote:
>
> > > Is this really the case? I noticed in the x86 version that setting
> > > the equivalent of the SE bit is allowed, how does the x86 get away
> > > with this while the PPC can't?
> >
> > These bits are optionally supported by processors. As I recall,
> > the 601 doesn't but I don't know of any others. You may find a
> > processor where they don't have any effect. I can't think of any
> > other reason.
>
> Slight correction: the 601 does have the SE bit but not the BE bit. The
> other important difference of the 601 is that it handles debug exceptions
> differently (different vector etc...).
>
> So at least the SE bit is present on all processors.
>
> Gabriel.
The SE bit is not present on at least some of the IBM PPC 4xx processors.
It is not present on the 405 processors. It is not present on the 403GCX.
(I did not check the other 403 variants.)
(This doesn't affect the discussion that led to the question about the SE
bit, but I thought I would let people know about the 4xx processors....)
-Frank
--
Frank Rowand <frank_rowand@mvista.com>
MontaVista Software, Inc
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2000-10-23 18:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-10-17 2:58 Allowing signal handlers to modify SE and BE Corey Minyard
2000-10-17 4:14 ` Dan Malek
2000-10-17 8:25 ` Gabriel Paubert
2000-10-17 14:55 ` Corey Minyard
2000-10-23 18:11 ` Frank Rowand [this message]
2000-10-18 0:01 ` Paul Mackerras
2000-10-18 1:38 ` Kevin Buettner
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