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Tsirkin" , "marcel.apfelbaum@gmail.com" References: <20260827004024.598351-1-tdave@nvidia.com> <20260827074733.340aeb0c@shazbot.org> <46b4544a-6e97-4433-b3e2-60cf43e62c7b@app.fastmail.com> From: Tushar Dave Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SA0PR11CA0128.namprd11.prod.outlook.com (2603:10b6:806:131::13) To DM4PR12MB9736.namprd12.prod.outlook.com (2603:10b6:8:225::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR12MB9736:EE_|CYXPR12MB9277:EE_ X-MS-Office365-Filtering-Correlation-Id: 489f1290-9d2a-4187-2fe6-08df08741de5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|23010399003|376014|366016|10067099003|56012099006|11063799006|3023799007|4143699003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: QQTFBkrIZ5wiUveHolz+adLhVC1lieOmKUamJ7PcXVEoGFJ4vCIylKEp4sBlCzdiFmkVbr8p+OPLrbq5MAeDQ7yKr5WNaCM104i/gTIbwFc2YgxbWnY2KgqF3XYBjCY/JEibVNdXPGw9+ct4/zbJ7LWtgFYIMUJUYGAU0v4H9LMvtoYBGOVag7IaUoHhMS+P7TIUg0wP13JkOuaGWxUKCEPGRwBTyDSbJkDEdtu9+GwfcN+2TQwACEMgUEltB0RkJQUHL9EA5jwvE7pjn2rPtHxWnt89+qOtUM2Fl2i9ppFIthfKbWDy5LUbch883v3Tw+32vuvzxElmHPoR1vI1F5PtaXT2cQNFAF8yGaKxmXX8QmzV6mM/UryfMcJxzubADHyIrIuVbscIYQvHZZh+7iKIUcvdQbNKkDlvt8uC8pwwupww3Vlv3KmSCYkoGf1ydXmAKNo9LuvJBdMye9tlogbU3EOa3Agf9qwo+uAhTP2C+23k1A5QczrDlzdUZoqw0kl5QN8o6HNxsv/gZoPFrUvClB8P23vdZdcBK/3cGYWZqqnwbADbGDjvw6dUAOMFvpZZXORHkuIiXjnv7jzfxUsbRngds9HM6Tro1w7A7ILIDJElQIKyXhqVZ88bzLkSvtOwODbDxAkWpF1lTQvpQbDQt3WaTodBkmACLDwMsbk= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 8/31/2026 8:42 AM, Gerd Hoffmann wrote: > Hi, > >>> Is this the reason we cannot rely on the Enhanced Allocation (EA) >>> capability here? >> >> AFAICT, this was explored on RFC v1. > >> EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL was suggested as the >> shorter path at the time, which is what this series uses. > > Essentially we have *two* problems to solve here. The first is how do > we get the fixed bar information from qemu to the firmware, and the > second is how we integrate that into edk2. > > So we could have a driver which parses EA and passes along the > information found to PciDxe using > EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. > > Not sure how much of a win that would be compared to adding EA support > to PciDxe directly given that the PciDxe bridge window logic needs > enhancements to properly handle fixed bars (as discussed below). Agreed, EA doesn't buy us much here; the bridge-window fix is needed either way. > >>> Agreed - if the bridge windows are not programmed correctly on the first >>> pass, there is something in the code that needs to be fixed. I don't think >>> papering over it like this is the right approach. >> >> That's a fair point. I did the window-sizing after PciBusDxe because I >> didn't want to touch existing PciBusDxe code too much. >> >> As per my understanding, PciBusDxe's enumeration splits into three phases: >> >> Phase 1 (PciHostBridgeEnumerator) walks the whole tree and calls >> CheckDevice() per device — by the time this phase finishes, every fixed >> BAR address is already known and cached on the device >> (PciBar[Bar].FixedBaseAddress). >> >> Phase 2 (PciHostBridgeResourceAllocator) prepares an address for every >> resource node in the tree — both individual BARs and bridge windows >> alike — purely from size and alignment; PCI_RESOURCE_NODE has no address >> field at all, so this is entirely blind to whether a fixed address was >> already required. >> >> Phase 3 (ProgramResource) then writes the actual PCI config-space >> registers, and by default it just writes whatever address Phase 2 >> prepared, for both BARs and bridge windows. The one exception is >> ProgramBar() — it specifically checks whether that particular BAR was >> marked fixed back in Phase 1, and if so, overrides Phase 2's prepared >> base address with the real fixed one. However, ProgramPpbApperture(), >> which writes the bridge's own window registers, has no equivalent >> override — it always writes whatever Phase 2 prepared, with no awareness >> of a fixed BAR anywhere underneath it. And that needs fixing, and for >> that I have to change the existing code. >> >> I think the fix would be to extend Phase 2's own sizing step >> (CalculateResourceAperture() in PciResourceSupport.c) to check for the >> already-known fixed address on each child and, when present, size and >> position the window as the exact union of those addresses instead of the >> blind size-only sum. Does that match the direction you had in mind, or >> is there a different integration point you'd suggest? > > Sounds about right, when propagating resource requirements up from > devices to bridges looking only at the size is not enough if we want > properly support pci bars at fixed locations. Thanks for confirming the direction. I'll implement this and post it as part of the next round. > > take care, > Gerd Thanks. -Tushar