From: Quinn Jensen <jensenq@Lineo.COM>
To: linux-mips@oss.sgi.com
Subject: Re: Linux on LSI EZ4102
Date: Wed, 18 Apr 2001 10:24:02 -0600 [thread overview]
Message-ID: <3ADDBFA2.7030608@Lineo.COM> (raw)
In-Reply-To: 15062.17293.403963.722517@valen.metzler
Are the caches two-way (or more)? If so, check
to see if the way select bit(s) are contiguous
with the offset for indexed cache operations.
If there is a hole, you have to flush in two
parts, or flush as if the cache was big enough
to span the hole.
Quinn
owner-linux-mips@oss.sgi.com wrote:
> Hi,
>
> does anybody have experience with the LSI EZ41XX line of MIPS cores
> and Linux, especially regarding the cache handling?
> They have a R3000-like MMU architecture and most of the MIPS2 command
> set but a totally different cache.
> Without cache enabled the Linux port I did works fine but with cache
> the ethernet driver and the MMU behave badly. I thought I implemented
> the flushing routines correctly but it seems I missed something.
> If somebody already did work on this architecture please let me know.
>
> Thanks,
>
> Ralph
next prev parent reply other threads:[~2001-04-18 16:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-04-13 0:08 Linux on LSI EZ4102 Ralph Metzler
2001-04-18 16:24 ` Quinn Jensen [this message]
2001-04-18 19:02 ` Ralph Metzler
2001-04-18 20:23 ` Keith M Wesolowski
2001-04-18 21:11 ` Alan Cox
2001-04-18 21:11 ` Alan Cox
2001-04-20 13:45 ` Ralf Baechle
2001-04-20 13:45 ` Ralf Baechle
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