From: Manfred Spraul <manfred@colorfullife.com>
To: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: SMP processor rework help needed
Date: Mon, 15 Oct 2001 19:16:16 +0200 [thread overview]
Message-ID: <3BCB19E0.64322276@colorfullife.com> (raw)
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> For intel the initial determination is made having the cpus race on
> the apic bus. The cpu that sends a message first gets the lowest
> apicid. Though I need to see how the P4 Xeon does it, as the apic
> bus is actually unused.
Huh?
24547202.pdf: (i.e. volume 3 of the ia32 SDM)
<<<<<<<<
The APIC ID register is loaded at power up by sampling configuration
data that is driven onto pins of the processor. For the Pentium 4 and P6
family processors, pins A11# and A12# and pins BR0# through BR3# are
sampled; for the Pentium processor, pins BE0# through BE3# are sampled.
<<<<<<
--
Manfred
next reply other threads:[~2001-10-15 17:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-10-15 17:16 Manfred Spraul [this message]
2001-10-15 21:39 ` SMP processor rework help needed Alan Cox
-- strict thread matches above, loose matches on Subject: below --
2001-10-14 20:23 Tommy Faasen
2001-10-14 20:33 ` Andi Kleen
2001-10-14 20:50 ` Gerhard Mack
2001-10-14 21:07 ` Andi Kleen
2001-10-15 15:20 ` Eric W. Biederman
2001-10-14 22:09 ` Tommy Faasen
2001-10-15 5:07 ` Pascal Schmidt
2001-10-15 21:25 ` Bill Davidsen
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