New API for non cache coherent ppc cpu's

[Armin Kuster <akuster@mvista.com>]

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To all NOT_COHERENT_CACHE users

About a month ago a new API made its way into the ppc,
consistent_sync_page.  For CONFIG_NOT_COHERENT_CACHE  processors,
requires
proper flushing of the page being used.  Please review and provide feed
back

-- armin




sample from patch

void consistent_sync_page(struct page *page, unsigned long offset,
size_t size, int direction)
{
        unsigned long start = (unsigned long)page->virtual;
        unsigned long end   = start + size;

        switch (direction) {
        case PCI_DMA_NONE:
                BUG();
        case PCI_DMA_FROMDEVICE:        /* invalidate only */
                invalidate_dcache_range(start, end);
                break;
        case PCI_DMA_TODEVICE:          /* writeback only */
                clean_dcache_range(start, end);
                break;
        case PCI_DMA_BIDIRECTIONAL:     /* writeback and invalidate */
                flush_dcache_range(start, end);
                break;
        }

 }

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