From: Jun Sun <jsun@mvista.com>
To: "TWEDE,ROGER (HP-Boise,ex1)" <roger_twede@hp.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: Mips IRQ support
Date: Tue, 22 Jan 2002 17:27:49 -0800 [thread overview]
Message-ID: <3C4E1195.9996C16@mvista.com> (raw)
In-Reply-To: CBD6266EA291D5118144009027AA63353F92B7@xboi05.boi.hp.com
"TWEDE,ROGER (HP-Boise,ex1)" wrote:
>
> Are there any plans to provide full MIPS irq support in the general mips irq
> code?
>
> The only machine that appears to attempt to fully support the MIPS interrupt
> set currently is the gt64120/momenco_ocelot machine.
>
> It uses the define CP0_S1_INTCONTROL ($20) to get at the upper interrupt
> lines ( > 8 ).
>
> Anyone else find that support for this MIPS hardware would be best placed in
> the standard irq code rather than each machine variant having to
> re-implement it itself (as the irq code was in the past).
>
Yes.
The best way is to provide hw_irq_controller structure for the extended CPU
IRQ feature. See arch/mips/kernel/irq_cpu.c file and its related config
option.
Jun
next prev parent reply other threads:[~2002-01-23 2:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-01-23 1:15 Mips IRQ support TWEDE,ROGER (HP-Boise,ex1)
2002-01-23 1:26 ` Pete Popov
2002-01-23 1:27 ` Jun Sun [this message]
2002-01-23 1:40 ` Jason Gunthorpe
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