diff -Naur --exclude=Entries --exclude=Makefile ../cvs_ref/alsa-kernel/include/cs46xx.h alsa-kernel/include/cs46xx.h --- ../cvs_ref/alsa-kernel/include/cs46xx.h Thu Aug 1 14:29:31 2002 +++ alsa-kernel/include/cs46xx.h Sun Aug 4 19:13:51 2002 @@ -195,6 +195,81 @@ #define BA1_FRSC 0x00030038 #define BA1_OMNI_MEM 0x000E0000 + + + +/* + * The following define the offsets of the AC97 shadow registers, which appear + * as a virtual extension to the base address register zero memory range. + */ +#define AC97_REG_OFFSET_MASK 0x0000007EL +#define AC97_CODEC_NUMBER_MASK 0x00003000L + +#define BA0_AC97_RESET 0x00001000L +#define BA0_AC97_MASTER_VOLUME 0x00001002L +#define BA0_AC97_HEADPHONE_VOLUME 0x00001004L +#define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L +#define BA0_AC97_MASTER_TONE 0x00001008L +#define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL +#define BA0_AC97_PHONE_VOLUME 0x0000100CL +#define BA0_AC97_MIC_VOLUME 0x0000100EL +#define BA0_AC97_LINE_IN_VOLUME 0x00001010L +#define BA0_AC97_CD_VOLUME 0x00001012L +#define BA0_AC97_VIDEO_VOLUME 0x00001014L +#define BA0_AC97_AUX_VOLUME 0x00001016L +#define BA0_AC97_PCM_OUT_VOLUME 0x00001018L +#define BA0_AC97_RECORD_SELECT 0x0000101AL +#define BA0_AC97_RECORD_GAIN 0x0000101CL +#define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL +#define BA0_AC97_GENERAL_PURPOSE 0x00001020L +#define BA0_AC97_3D_CONTROL 0x00001022L +#define BA0_AC97_MODEM_RATE 0x00001024L +#define BA0_AC97_POWERDOWN 0x00001026L +#define BA0_AC97_EXT_AUDIO_ID 0x00001028L +#define BA0_AC97_EXT_AUDIO_POWER 0x0000102AL +#define BA0_AC97_PCM_FRONT_DAC_RATE 0x0000102CL +#define BA0_AC97_PCM_SURR_DAC_RATE 0x0000102EL +#define BA0_AC97_PCM_LFE_DAC_RATE 0x00001030L +#define BA0_AC97_PCM_LR_ADC_RATE 0x00001032L +#define BA0_AC97_MIC_ADC_RATE 0x00001034L +#define BA0_AC97_6CH_VOL_C_LFE 0x00001036L +#define BA0_AC97_6CH_VOL_SURROUND 0x00001038L +#define BA0_AC97_RESERVED_3A 0x0000103AL +#define BA0_AC97_EXT_MODEM_ID 0x0000103CL +#define BA0_AC97_EXT_MODEM_POWER 0x0000103EL +#define BA0_AC97_LINE1_CODEC_RATE 0x00001040L +#define BA0_AC97_LINE2_CODEC_RATE 0x00001042L +#define BA0_AC97_HANDSET_CODEC_RATE 0x00001044L +#define BA0_AC97_LINE1_CODEC_LEVEL 0x00001046L +#define BA0_AC97_LINE2_CODEC_LEVEL 0x00001048L +#define BA0_AC97_HANDSET_CODEC_LEVEL 0x0000104AL +#define BA0_AC97_GPIO_PIN_CONFIG 0x0000104CL +#define BA0_AC97_GPIO_PIN_TYPE 0x0000104EL +#define BA0_AC97_GPIO_PIN_STICKY 0x00001050L +#define BA0_AC97_GPIO_PIN_WAKEUP 0x00001052L +#define BA0_AC97_GPIO_PIN_STATUS 0x00001054L +#define BA0_AC97_MISC_MODEM_AFE_STAT 0x00001056L +#define BA0_AC97_RESERVED_58 0x00001058L +#define BA0_AC97_CRYSTAL_REV_N_FAB_ID 0x0000105AL +#define BA0_AC97_TEST_AND_MISC_CTRL 0x0000105CL +#define BA0_AC97_AC_MODE 0x0000105EL +#define BA0_AC97_MISC_CRYSTAL_CONTROL 0x00001060L +#define BA0_AC97_LINE1_HYPRID_CTRL 0x00001062L +#define BA0_AC97_VENDOR_RESERVED_64 0x00001064L +#define BA0_AC97_VENDOR_RESERVED_66 0x00001066L +#define BA0_AC97_SPDIF_CONTROL 0x00001068L +#define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL +#define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL +#define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL +#define BA0_AC97_VENDOR_RESERVED_70 0x00001070L +#define BA0_AC97_VENDOR_RESERVED_72 0x00001072L +#define BA0_AC97_VENDOR_RESERVED_74 0x00001074L +#define BA0_AC97_CAL_ADDRESS 0x00001076L +#define BA0_AC97_CAL_DATA 0x00001078L +#define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL +#define BA0_AC97_VENDOR_ID1 0x0000107CL +#define BA0_AC97_VENDOR_ID2 0x0000107EL + /* * The following defines are for the flags in the host interrupt status * register. @@ -1629,10 +1704,11 @@ #define POWER_DOWN_ALL 0x7f0f /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */ -#define MAX_NR_AC97 4 -#define CS46XX_PRIMARY_CODEC_INDEX 0 +#define MAX_NR_AC97 4 +#define CS46XX_PRIMARY_CODEC_INDEX 0 #define CS46XX_SECONDARY_CODEC_INDEX 1 #define CS46XX_SECONDARY_CODEC_OFFSET 0x80 +#define CS46XX_DSP_CAPTURE_CHANNEL 1 /* * diff -Naur --exclude=Entries --exclude=Makefile ../cvs_ref/alsa-kernel/pci/cs46xx/cs46xx_lib.c alsa-kernel/pci/cs46xx/cs46xx_lib.c --- ../cvs_ref/alsa-kernel/pci/cs46xx/cs46xx_lib.c Sun Aug 4 19:12:45 2002 +++ alsa-kernel/pci/cs46xx/cs46xx_lib.c Sun Aug 4 20:53:30 2002 @@ -1167,7 +1167,7 @@ for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { if (i <= 15) { if ( status1 & (1 << i) ) { - if (i == 1) { + if (i == CS46XX_DSP_CAPTURE_CHANNEL) { if (chip->capt.substream) snd_pcm_period_elapsed(chip->capt.substream); } else { @@ -2449,6 +2449,106 @@ { } + +#ifdef CONFIG_SND_CS46XX_NEW_DSP +static int voyetra_setup_eapd_slot(cs46xx_t *chip) +{ + int i; + u32 idx; + u16 modem_power,pin_config,logic_type,valid_slots,status; + + snd_printd ("cs46xx: cs46xx_setup_eapd_slot()+\n"); + /* + * Clear PRA. The Bonzo chip will be used for GPIO not for modem + * stuff. + */ + if(chip->nr_ac97_codecs != 2) + { + snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n"); + return -EINVAL; + } + + modem_power = snd_cs46xx_codec_read (chip, + BA0_AC97_EXT_MODEM_POWER, + CS46XX_SECONDARY_CODEC_INDEX); + modem_power &=0xFEFF; + + snd_cs46xx_codec_write(chip, + BA0_AC97_EXT_MODEM_POWER, modem_power, + CS46XX_SECONDARY_CODEC_INDEX); + + /* + * Set GPIO pin's 7 and 8 so that they are configured for output. + */ + pin_config = snd_cs46xx_codec_read (chip, + BA0_AC97_GPIO_PIN_CONFIG, + CS46XX_SECONDARY_CODEC_INDEX); + pin_config &=0x27F; + + snd_cs46xx_codec_write(chip, + BA0_AC97_GPIO_PIN_CONFIG, pin_config, + CS46XX_SECONDARY_CODEC_INDEX); + + /* + * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. + */ + + logic_type = snd_cs46xx_codec_read(chip, BA0_AC97_GPIO_PIN_TYPE, + CS46XX_SECONDARY_CODEC_INDEX); + logic_type &=0x27F; + snd_cs46xx_codec_write (chip, BA0_AC97_GPIO_PIN_TYPE, logic_type, + CS46XX_SECONDARY_CODEC_INDEX); + + valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); + valid_slots |= 0x200; + snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); + + /* + * Fill slots 12 with the correct value for the GPIO pins. + */ + for(idx = 0x90; idx <= 0x9F; idx++) { + + /* + * Initialize the fifo so that bits 7 and 8 are on. + * + * Remember that the GPIO pins in bonzo are shifted by 4 bits to + * the left. 0x1800 corresponds to bits 7 and 8. + */ + snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); + + /* + * Make sure the previous FIFO write operation has completed. + */ + for(i = 0; i < 5; i++){ + status = snd_cs46xx_peekBA0(chip, BA0_SERBST); + + if( !(status & SERBST_WBSY) ) { + break; + } + mdelay(100); + } + + if(status & SERBST_WBSY) { + snd_printk( KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() " \ + "Failure to write the GPIO pins for slot 12.\n"); + return -EINVAL; + } + + /* + * Write the serial port FIFO index. + */ + snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); + + /* + * Tell the serial port to load the new value into the FIFO location. + */ + snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); + } + + return 0; +} +#endif + /* * Crystal EAPD mode */ @@ -2479,6 +2579,12 @@ snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->eapd_switch->id); } + +#ifdef CONFIG_SND_CS46XX_NEW_DSP + if (chip->amplifier && !old) { + voyetra_setup_eapd_slot(chip); + } +#endif } diff -Naur --exclude=Entries --exclude=Makefile ../cvs_ref/alsa-kernel/pci/cs46xx/dsp_spos.c alsa-kernel/pci/cs46xx/dsp_spos.c --- ../cvs_ref/alsa-kernel/pci/cs46xx/dsp_spos.c Thu Aug 1 14:30:53 2002 +++ alsa-kernel/pci/cs46xx/dsp_spos.c Sun Aug 4 20:13:17 2002 @@ -735,7 +735,7 @@ snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n"); col = 0; - for (i = 0x1200;i < 0x1240; i += sizeof(u32),col ++) { + for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) { if (col == 4) { snd_iprintf(buffer,"\n"); col = 0; @@ -748,9 +748,9 @@ snd_iprintf(buffer,"%08X ",readl(dst + i)); } - snd_iprintf(buffer,"\n...\n"); + snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n"); col = 0; - for (i = 0x12D0;i < 0x1310; i += sizeof(u32),col ++) { + for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) { if (col == 4) { snd_iprintf(buffer,"\n"); col = 0; @@ -763,20 +763,23 @@ snd_iprintf(buffer,"%08X ",readl(dst + i)); } - snd_iprintf(buffer,"\n"); -} + snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n"); + col = 0; + for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) { + if (col == 4) { + snd_iprintf(buffer,"\n"); + col = 0; + } -#if 0 -static void snd_ac97_proc_regs_read_main(ac97_t *ac97, snd_info_buffer_t * buffer, int subidx) -{ - int reg, val; + if (col == 0) { + snd_iprintf(buffer, "%04X ",i); + } - for (reg = 0; reg < 0x80; reg += 2) { - val = snd_ac97_read(ac97, reg); - snd_iprintf(buffer, "%i:%02x = %04x\n", subidx, reg, val); + snd_iprintf(buffer,"%08X ",readl(dst + i)); } + + snd_iprintf(buffer,"\n"); } -#endif int cs46xx_dsp_proc_init (snd_card_t * card, cs46xx_t *chip) { @@ -1349,9 +1352,9 @@ /* create codec in */ codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0, - MIX_SAMPLE_BUF1, - CODECIN_SCB_ADDR,codec_out_scb, - SCB_ON_PARENT_NEXT_SCB); + CODEC_INPUT_BUF1, + CODECIN_SCB_ADDR,codec_out_scb, + SCB_ON_PARENT_NEXT_SCB); if (!codec_in_scb) goto _fail_end; /* create write back scb */ diff -Naur --exclude=Entries --exclude=Makefile ../cvs_ref/alsa-kernel/pci/cs46xx/dsp_spos_scb_lib.c alsa-kernel/pci/cs46xx/dsp_spos_scb_lib.c --- ../cvs_ref/alsa-kernel/pci/cs46xx/dsp_spos_scb_lib.c Thu Aug 1 15:51:28 2002 +++ alsa-kernel/pci/cs46xx/dsp_spos_scb_lib.c Sun Aug 4 20:10:16 2002 @@ -697,7 +697,7 @@ DMA_RQ_C2_AC_NONE + DMA_RQ_C2_SIGNAL_DEST_PINGPONG + - 1, + CS46XX_DSP_CAPTURE_CHANNEL, DMA_RQ_SD_SP_SAMPLE_ADDR + mix_buffer_addr, 0x0 @@ -1108,7 +1108,7 @@ /* virtual channel reserved for capture */ - if (i == 1) continue; + if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue; if (ins->pcm_channels[i].active) { if (!src_scb && ins->pcm_channels[i].sample_rate == sample_rate) {