diff for duplicates of <3DD8014B.D88A6C34@paradyne.com> diff --git a/a/1.txt b/N1/1.txt index 6c212e1..ca5d6cd 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,49 +1,52 @@ + Tom + Joakim, we're doing a release soon over here at sensors/i2c, do you want this checked in as-is, with mods, or not at all? Joakim Tjernlund wrote: -> +> > > > > > > Here is a patch against the PPC 2.4 devel tree for the i2c-algo-8xx.c > > > > Can you please split this into logical chunks, or give me a list of each > > fix in here? Thanks. -> +> > ohh, kind of hard to remember all that went into that patch. The path > has evoled over many days, but I can try summarize. I have tested this code > pretty well it does not fail for me. Speed has been between 10-150KHz. The > old code fails as soon you start to stress it a little. -> +> > - replace invalidate_dcache_range with flush_dcache_range, since buffers are > NOT cache aligned. flush will write to memory AND invalidate the cache. -> +> > - move the chip errata stuff from irq routine into read/write routines. Made > it default off since it causes lock ups on my I2C device. I think it causes > a too short STOP condition. If enabled I2C will behave better than before, but > may still cause problems if the read/write is interrupted with a signal while > microcode is enabled. -> +> > - set default speed to 60 KHz instead. -> +> > - missing/faulty initialization of parameter ram when I2C micro patch is active. -> +> > - replaced assingments with mask operations with relevant bits. Example: > /* Shut down IIC. */ > i2c->i2c_i2mod = 0; > i2c->i2c_i2mod &= ~1; -> +> > - When reading from I2C device, let the receive BD generate interrupt instead of > the dummy trasmit. This is important since the TX interrupt will be too early sometimes, before > the RX BD has closed. There is one case where the RX irq is before the TX irq, if iic_mrblr is set > to match the number of bytes to read. Therefore must the iic_mrblr be one byte larger than > the expected number of bytes. -> +> > - busy wait for small transfers since it's faster. -> +> > - save_flags(flags); cli(); cleanups -> +> > - interruptible_sleep_on_timeout() instead of interruptible_sleep_on() so it won't hang forever if an > irq is lost. -> +> > Jocke + +** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/ diff --git a/a/content_digest b/N1/content_digest index bd0fa1d..1246bb9 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,61 +1,64 @@ "ref\0IGEFJKJNHJDCBKALBJLLMEFNFHAA.joakim.tjernlund@lumentis.se\0" - "From\0mds@paradyne.com (Mark D. Studebaker)\0" - "Subject\08xx i2c refers to unspecified chip errata\0" - "Date\0Thu, 19 May 2005 06:23:41 +0000\0" + "From\0Mark D. Studebaker <mds@paradyne.com>\0" + "Subject\0Re: 8xx i2c refers to unspecified chip errata\0" + "Date\0Sun, 17 Nov 2002 15:51:23 -0500\0" "To\0joakim.tjernlund@lumentis.se\0" "Cc\0Tom Rini <trini@kernel.crashing.org>" linuxppc-embedded@lists.linuxppc.org " sensors@stimpy.netroedge.com\0" "\00:1\0" "b\0" + "\n" "Tom + Joakim,\n" "we're doing a release soon over here at sensors/i2c,\n" "do you want this checked in as-is, with mods, or not at all?\n" "\n" "Joakim Tjernlund wrote:\n" - "> \n" + ">\n" "> > >\n" "> > > Here is a patch against the PPC 2.4 devel tree for the i2c-algo-8xx.c\n" "> >\n" "> > Can you please split this into logical chunks, or give me a list of each\n" "> > fix in here? Thanks.\n" - "> \n" + ">\n" "> ohh, kind of hard to remember all that went into that patch. The path\n" "> has evoled over many days, but I can try summarize. I have tested this code\n" "> pretty well it does not fail for me. Speed has been between 10-150KHz. The\n" "> old code fails as soon you start to stress it a little.\n" - "> \n" + ">\n" "> - replace invalidate_dcache_range with flush_dcache_range, since buffers are\n" "> NOT cache aligned. flush will write to memory AND invalidate the cache.\n" - "> \n" + ">\n" "> - move the chip errata stuff from irq routine into read/write routines. Made\n" "> it default off since it causes lock ups on my I2C device. I think it causes\n" "> a too short STOP condition. If enabled I2C will behave better than before, but\n" "> may still cause problems if the read/write is interrupted with a signal while\n" "> microcode is enabled.\n" - "> \n" + ">\n" "> - set default speed to 60 KHz instead.\n" - "> \n" + ">\n" "> - missing/faulty initialization of parameter ram when I2C micro patch is active.\n" - "> \n" + ">\n" "> - replaced assingments with mask operations with relevant bits. Example:\n" "> /* Shut down IIC. */\n" "> i2c->i2c_i2mod = 0;\n" "> i2c->i2c_i2mod &= ~1;\n" - "> \n" + ">\n" "> - When reading from I2C device, let the receive BD generate interrupt instead of\n" "> the dummy trasmit. This is important since the TX interrupt will be too early sometimes, before\n" "> the RX BD has closed. There is one case where the RX irq is before the TX irq, if iic_mrblr is set\n" "> to match the number of bytes to read. Therefore must the iic_mrblr be one byte larger than\n" "> the expected number of bytes.\n" - "> \n" + ">\n" "> - busy wait for small transfers since it's faster.\n" - "> \n" + ">\n" "> - save_flags(flags); cli(); cleanups\n" - "> \n" + ">\n" "> - interruptible_sleep_on_timeout() instead of interruptible_sleep_on() so it won't hang forever if an\n" "> irq is lost.\n" - "> \n" - > Jocke + ">\n" + "> Jocke\n" + "\n" + ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/ -526da8954434a307c90133bf4e0672a27871283b1b339a630fa683c59e35ab6a +34307ebe0564a16f3b21f7be04439bfeb54b822e136627a6172f693553ddd02a
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