From: Dave Wilhardt <wilhardt@synergymicro.com>
To: Dan Malek <dan@embeddededge.com>
Cc: Gabriel Paubert <paubert@iram.es>,
wilhardt@synergymicro.com, linuxppc-dev@lists.linuxppc.org
Subject: Re: MPC7455 and lwarx
Date: Wed, 27 Nov 2002 09:11:37 -0800 [thread overview]
Message-ID: <3DE4FCC9.E62EF5B1@synergymicro.com> (raw)
In-Reply-To: 3DE4DAE1.9060602@embeddededge.com
>
>
> Why do you want to use these instructions on a data space that isn't
> cached? Further, why are you running this class of processor with
> uncached memory?
>
I have a "shared memory" region that is used between VME boards in
a chassis. The "master pool" is located on the system controller in DRAM.
In order to maintain coherency between the boards, I have marked the region
as non cached. This was fine for non-MPC745x boards. Time for a redesign...
- Dave
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2002-11-27 17:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-11-26 22:00 MPC7455 and lwarx Dave Wilhardt
2002-11-27 13:00 ` Gabriel Paubert
2002-11-27 14:46 ` Dan Malek
2002-11-27 17:11 ` Dave Wilhardt [this message]
2002-11-27 17:32 ` Gabriel Paubert
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