Index: arch/mips/kernel/unaligned.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/kernel/unaligned.c,v
retrieving revision 1.15.2.7
diff -u -r1.15.2.7 unaligned.c
--- arch/mips/kernel/unaligned.c	7 Nov 2002 23:50:11 -0000	1.15.2.7
+++ arch/mips/kernel/unaligned.c	4 Dec 2002 12:37:38 -0000
@@ -494,10 +494,10 @@
 
 	/*
 	 * Did we catch a fault trying to load an instruction?
-	 * This also catches attempts to activate MIPS16 code on
-	 * CPUs which don't support it.
+	 * Or are we running in MIPS16 mode?
 	 */
-	if (regs->cp0_badvaddr == regs->cp0_epc)
+	if ((regs->cp0_badvaddr == regs->cp0_epc) ||
+	    (regs->cp0_epc & 0x1))
 		goto sigbus;
 
 	pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0);
Index: arch/mips64/kernel/unaligned.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.6.2.6
diff -u -r1.6.2.6 unaligned.c
--- arch/mips64/kernel/unaligned.c	7 Nov 2002 23:50:11 -0000	1.6.2.6
+++ arch/mips64/kernel/unaligned.c	4 Dec 2002 12:37:40 -0000
@@ -494,10 +494,10 @@
 
 	/*
 	 * Did we catch a fault trying to load an instruction?
-	 * This also catches attempts to activate MIPS16 code on
-	 * CPUs which don't support it.
+	 * Or are we running in MIPS16 mode?
 	 */
-	if (regs->cp0_badvaddr == regs->cp0_epc)
+	if ((regs->cp0_badvaddr == regs->cp0_epc) ||
+	    (regs->cp0_epc & 0x1))
 		goto sigbus;
 
 	pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0);