From: Fuxin Zhang <fxzhang@ict.ac.cn>
To: MAKE FUN PRANK CALLS <linux-mips@linux-mips.org>
Subject: RM7k cache_flush_sigtramp
Date: Thu, 31 Jul 2003 09:56:08 +0800 [thread overview]
Message-ID: <3F287738.1040203@ict.ac.cn> (raw)
hi,
r4k_cache_flush_sigtrap seems not enough for RM7000 cpus because
there is a writebuffer between L1 dcache & L2 cache,so the written back
block may not be seen by icache. This small patch fixes crashes of my
Xserver
on ev64240.
--- r4kcache.h.ori 2003-07-31 09:51:01.000000000 +0800
+++ r4kcache.h 2003-07-31 09:51:57.000000000 +0800
@@ -94,6 +94,9 @@
".set noreorder\n\t"
".set mips3\n"
"1:\tcache %0,(%1)\n"
+#ifdef CONFIG_CPU_RM7000
+ "sync\n\t"
+#endif
"2:\t.set mips0\n\t"
".set reorder\n\t"
".section\t__ex_table,\"a\"\n\t"
next reply other threads:[~2003-07-31 1:56 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-31 1:56 Fuxin Zhang [this message]
2003-07-31 11:46 ` RM7k cache_flush_sigtramp Ralf Baechle
2003-07-31 12:57 ` Fuxin Zhang
-- strict thread matches above, loose matches on Subject: below --
2003-07-31 16:50 Adam Kiepul
2003-08-01 0:40 ` Fuxin Zhang
2003-08-01 3:01 ` Ralf Baechle
2003-08-01 4:59 ` Fuxin Zhang
2003-08-01 7:51 ` Dominic Sweetman
2003-08-01 7:51 ` Dominic Sweetman
2003-08-01 9:26 ` Ralf Baechle
2003-08-01 14:18 ` Fuxin Zhang
2003-08-02 17:02 ` Ralf Baechle
2003-08-04 8:45 ` Dominic Sweetman
2003-08-04 11:51 ` Maciej W. Rozycki
2003-08-01 15:42 Adam Kiepul
2003-08-04 3:38 ` Fuxin Zhang
2003-08-06 11:00 ` Fuxin Zhang
2003-08-06 11:55 ` Ralf Baechle
2003-08-06 12:52 ` Fuxin Zhang
2003-08-06 14:45 ` Ralf Baechle
2003-08-06 15:04 ` Fuxin Zhang
2003-08-06 22:30 ` Ralf Baechle
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