From: Philippe Elie <phil.el@wanadoo.fr>
To: Jamie Lokier <jamie@shareable.org>
Cc: michaelc <michaelc@turbolinux.com.cn>, linux-kernel@vger.kernel.org
Subject: Re: about PENTIUM4 cache line
Date: Sun, 17 Aug 2003 22:52:45 +0000 [thread overview]
Message-ID: <3F40073D.6090202@wanadoo.fr> (raw)
In-Reply-To: 20030817202534.GC3543@mail.jlokier.co.uk
Jamie Lokier wrote:
> michaelc wrote:
>
>> I read the Intel IA-32 developer's manual recently, and I found
>> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>> wide, but the thing make me confused is that the default value
>> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>> not 6? Any expanation about this would be appreciated!
>
>
> I don't recall seeing an answer to this.
> Was there one?
There is some confusion about P4 cache line size but
Intel Software Developer's Manual VOL 1
Page 2.12, Par 2.6:
"128-byte cache line size
- Two 64-byte sectors"
regards,
Philippe Elie
prev parent reply other threads:[~2003-08-17 20:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-03-09 9:03 about PENTIUM4 cache line michaelc
2001-08-08 11:52 ` shutdown on pressing the ATX power button Sergei Haller
2001-08-09 17:56 ` Pavel Machek
2003-08-17 20:25 ` about PENTIUM4 cache line Jamie Lokier
2003-08-17 20:36 ` David B. Stevens
2003-08-17 20:45 ` Dave Jones
2003-08-17 20:58 ` David B. Stevens
2003-08-17 20:42 ` Dave Jones
2003-08-17 22:52 ` Philippe Elie [this message]
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