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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485246fd127sm140956635e9.6.2026.03.09.11.05.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Mar 2026 11:05:28 -0700 (PDT) Message-ID: <3cd7007b-b57f-4e4d-a354-75aab41eddeb@redhat.com> Date: Mon, 9 Mar 2026 19:05:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 30/32] hw/arm/smmuv3-accel: Introduce helper to query CMDQV type To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, clg@redhat.com, alex@shazbot.org, nicolinc@nvidia.com, nathanc@nvidia.com, mochs@nvidia.com, jan@nvidia.com, jgg@nvidia.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, kjaju@nvidia.com, phrdina@redhat.com References: <20260226105056.897-1-skolothumtho@nvidia.com> <20260226105056.897-31-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20260226105056.897-31-skolothumtho@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: _FCEcXm1F8FIa6Hs1nJM8PcbAtcCaE23WCQs9eXZnqw_1773079531 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 2/26/26 11:50 AM, Shameer Kolothum wrote: > Introduce a SMMUv3AccelCmdqvType enum and a helper to query the > CMDQV implementation type associated with an accelerated SMMUv3 > instance. > > A subsequent patch will use this helper when generating the > Tegra241 CMDQV DSDT. > > Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Eric > --- > hw/arm/smmuv3-accel.h | 7 +++++++ > hw/arm/smmuv3-accel-stubs.c | 5 +++++ > hw/arm/smmuv3-accel.c | 12 ++++++++++++ > hw/arm/tegra241-cmdqv.c | 6 ++++++ > 4 files changed, 30 insertions(+) > > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > index c349981e79..6d21788006 100644 > --- a/hw/arm/smmuv3-accel.h > +++ b/hw/arm/smmuv3-accel.h > @@ -15,6 +15,11 @@ > #include > #endif > > +typedef enum SMMUv3AccelCmdqvType { > + SMMUV3_CMDQV_NONE = 0, > + SMMUV3_CMDQV_TEGRA241, > +} SMMUv3AccelCmdqvType; > + > /* > * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to > * support multiple VCMDQs with virtualization capabilities. > @@ -30,6 +35,7 @@ typedef struct SMMUv3AccelCmdqvOps { > void (*free_viommu)(SMMUv3State *s); > bool (*alloc_veventq)(SMMUv3State *s, Error **errp); > void (*free_veventq)(SMMUv3State *s); > + SMMUv3AccelCmdqvType (*get_type)(void); > void (*reset)(SMMUv3State *s); > } SMMUv3AccelCmdqvOps; > > @@ -73,5 +79,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); > bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type, > void *buf, size_t size, Error **errp); > void smmuv3_accel_reset(SMMUv3State *s); > +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj); > > #endif /* HW_ARM_SMMUV3_ACCEL_H */ > diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c > index 1d5d3bb10c..5ca94d605f 100644 > --- a/hw/arm/smmuv3-accel-stubs.c > +++ b/hw/arm/smmuv3-accel-stubs.c > @@ -55,3 +55,8 @@ void smmuv3_accel_idr_override(SMMUv3State *s) > void smmuv3_accel_reset(SMMUv3State *s) > { > } > + > +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) > +{ > + return SMMUV3_CMDQV_NONE; > +} > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index 9a570b8af9..585b460943 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -998,6 +998,18 @@ static void smmuv3_accel_as_init(SMMUv3State *s) > address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); > } > > +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) > +{ > + SMMUv3State *s = ARM_SMMUV3(obj); > + SMMUv3AccelState *accel = s->s_accel; > + > + if (!accel || !accel->cmdqv_ops || !accel->cmdqv_ops->get_type) { > + return SMMUV3_CMDQV_NONE; > + } > + > + return accel->cmdqv_ops->get_type(); > +} > + > bool smmuv3_accel_init(SMMUv3State *s, Error **errp) > { > SMMUState *bs = ARM_SMMU(s); > diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c > index a379341c0a..42d7dbfde7 100644 > --- a/hw/arm/tegra241-cmdqv.c > +++ b/hw/arm/tegra241-cmdqv.c > @@ -736,6 +736,11 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) > return true; > } > > +static SMMUv3AccelCmdqvType tegra241_cmdqv_get_type(void) > +{ > + return SMMUV3_CMDQV_TEGRA241; > +}; > + > static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, > Error **errp) > { > @@ -778,6 +783,7 @@ static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops = { > .free_viommu = tegra241_cmdqv_free_viommu, > .alloc_veventq = tegra241_cmdqv_alloc_veventq, > .free_veventq = tegra241_cmdqv_free_veventq, > + .get_type = tegra241_cmdqv_get_type, > .reset = tegra241_cmdqv_reset, > }; >