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Thu, 05 Jun 2025 06:24:42 -0700 (PDT) Received: from [192.168.68.110] ([177.188.133.196]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-235e5aafa94sm24213645ad.186.2025.06.05.06.24.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jun 2025 06:24:41 -0700 (PDT) Message-ID: <3d1b8880-bf87-453c-9e16-06312337ffcb@ventanamicro.com> Date: Thu, 5 Jun 2025 10:24:36 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class To: Zhenzhong Duan , qemu-devel@nongnu.org Cc: chao.p.peng@intel.com, david@redhat.com, Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" References: <20250605102311.148171-1-zhenzhong.duan@intel.com> <20250605102311.148171-6-zhenzhong.duan@intel.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250605102311.148171-6-zhenzhong.duan@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 6/5/25 7:23 AM, Zhenzhong Duan wrote: > RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed > parent class, class_init on them may corrupt their parent class > fields. > > It's lucky that parent_realize and parent_phases are not initialized > or used until now, so just remove the definitions. They can be added > back when really necessary. > > Signed-off-by: Zhenzhong Duan > --- Reviewed-by: Daniel Henrique Barboza > include/hw/riscv/iommu.h | 6 ++---- > hw/riscv/riscv-iommu-pci.c | 6 ------ > hw/riscv/riscv-iommu-sys.c | 6 ------ > 3 files changed, 2 insertions(+), 16 deletions(-) > > diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h > index b03339d75c..8a8acfc3f0 100644 > --- a/include/hw/riscv/iommu.h > +++ b/include/hw/riscv/iommu.h > @@ -30,14 +30,12 @@ typedef struct RISCVIOMMUState RISCVIOMMUState; > typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; > > #define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci" > -OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI) > +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) > typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; > -typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass; > > #define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" > -OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS) > +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) > typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; > -typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass; > > #define FDT_IRQ_TYPE_EDGE_LOW 1 > > diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c > index 1f44eef74e..cdb4a7a8f0 100644 > --- a/hw/riscv/riscv-iommu-pci.c > +++ b/hw/riscv/riscv-iommu-pci.c > @@ -68,12 +68,6 @@ typedef struct RISCVIOMMUStatePci { > RISCVIOMMUState iommu; /* common IOMMU state */ > } RISCVIOMMUStatePci; > > -struct RISCVIOMMUPciClass { > - /*< public >*/ > - DeviceRealize parent_realize; > - ResettablePhases parent_phases; > -}; > - > /* interrupt delivery callback */ > static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) > { > diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c > index 74e76b94a5..e34d00aef6 100644 > --- a/hw/riscv/riscv-iommu-sys.c > +++ b/hw/riscv/riscv-iommu-sys.c > @@ -53,12 +53,6 @@ struct RISCVIOMMUStateSys { > uint8_t *msix_pba; > }; > > -struct RISCVIOMMUSysClass { > - /*< public >*/ > - DeviceRealize parent_realize; > - ResettablePhases parent_phases; > -}; > - > static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, > unsigned size) > {