From: Konstantin Ananyev <konstantin.ananyev@huawei.com>
To: Stephen Hemminger <stephen@networkplumber.org>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: Wathsala Vithanage <wathsala.vithanage@arm.com>,
Bibo Mao <maobibo@loongson.cn>,
David Christensen <drc@linux.ibm.com>,
Sun Yuechi <sunyuechi@iscas.ac.cn>,
Bruce Richardson <bruce.richardson@intel.com>
Subject: RE: [PATCH v4 01/27] eal: use intrinsics for rte_atomic on all platforms
Date: Mon, 1 Jun 2026 18:23:41 +0000 [thread overview]
Message-ID: <3e30b54a14ab437c93277895e3cebc2a@huawei.com> (raw)
In-Reply-To: <20260526232542.620966-2-stephen@networkplumber.org>
> Next step is to deprecate the rte_atomicNN_*() family. Rather than
> maintaining both the inline asm and intrinsic fallbacks, drop the
> asm paths and use intrinsics everywhere.
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
> lib/eal/arm/include/rte_atomic_32.h | 4 -
> lib/eal/arm/include/rte_atomic_64.h | 4 -
> lib/eal/include/generic/rte_atomic.h | 76 +---------
> lib/eal/loongarch/include/rte_atomic.h | 4 -
> lib/eal/ppc/include/rte_atomic.h | 173 -----------------------
> lib/eal/riscv/include/rte_atomic.h | 4 -
> lib/eal/x86/include/rte_atomic.h | 172 ----------------------
> lib/eal/x86/include/rte_atomic_32.h | 188 -------------------------
> lib/eal/x86/include/rte_atomic_64.h | 157 ---------------------
> 9 files changed, 6 insertions(+), 776 deletions(-)
>
> diff --git a/lib/eal/arm/include/rte_atomic_32.h
> b/lib/eal/arm/include/rte_atomic_32.h
> index 0b9a0dfa30..696a539fef 100644
> --- a/lib/eal/arm/include/rte_atomic_32.h
> +++ b/lib/eal/arm/include/rte_atomic_32.h
> @@ -5,10 +5,6 @@
> #ifndef _RTE_ATOMIC_ARM32_H_
> #define _RTE_ATOMIC_ARM32_H_
>
> -#ifndef RTE_FORCE_INTRINSICS
> -# error Platform must be built with RTE_FORCE_INTRINSICS
> -#endif
> -
> #include "generic/rte_atomic.h"
>
> #ifdef __cplusplus
> diff --git a/lib/eal/arm/include/rte_atomic_64.h
> b/lib/eal/arm/include/rte_atomic_64.h
> index 181bb60929..9f790238df 100644
> --- a/lib/eal/arm/include/rte_atomic_64.h
> +++ b/lib/eal/arm/include/rte_atomic_64.h
> @@ -6,10 +6,6 @@
> #ifndef _RTE_ATOMIC_ARM64_H_
> #define _RTE_ATOMIC_ARM64_H_
>
> -#ifndef RTE_FORCE_INTRINSICS
> -# error Platform must be built with RTE_FORCE_INTRINSICS
> -#endif
> -
> #include "generic/rte_atomic.h"
> #include <rte_branch_prediction.h>
> #include <rte_debug.h>
> diff --git a/lib/eal/include/generic/rte_atomic.h
> b/lib/eal/include/generic/rte_atomic.h
> index 0a4f3f8528..292e52fade 100644
> --- a/lib/eal/include/generic/rte_atomic.h
> +++ b/lib/eal/include/generic/rte_atomic.h
> @@ -187,13 +187,11 @@ static inline void
> rte_atomic_thread_fence(rte_memory_order memorder);
> static inline int
> rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int
> rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
> {
> return __sync_bool_compare_and_swap(dst, exp, src);
> }
> -#endif
>
> /**
> * Atomic exchange.
> @@ -211,15 +209,11 @@ rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t
> exp, uint16_t src)
> * The original value at that location
> */
> static inline uint16_t
> -rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val);
> -
> -#ifdef RTE_FORCE_INTRINSICS
> -static inline uint16_t
> rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
> {
> - return rte_atomic_exchange_explicit(dst, val,
> rte_memory_order_seq_cst);
> + return rte_atomic_exchange_explicit((volatile __rte_atomic uint16_t
> *)dst,
> + val, rte_memory_order_seq_cst);
> }
> -#endif
>
> /**
> * The atomic counter structure.
> @@ -312,13 +306,11 @@ rte_atomic16_sub(rte_atomic16_t *v, int16_t dec)
> static inline void
> rte_atomic16_inc(rte_atomic16_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic16_inc(rte_atomic16_t *v)
> {
> rte_atomic16_add(v, 1);
> }
> -#endif
>
> /**
> * Atomically decrement a counter by one.
> @@ -329,13 +321,11 @@ rte_atomic16_inc(rte_atomic16_t *v)
> static inline void
> rte_atomic16_dec(rte_atomic16_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic16_dec(rte_atomic16_t *v)
> {
> rte_atomic16_sub(v, 1);
> }
> -#endif
>
> /**
> * Atomically add a 16-bit value to a counter and return the result.
> @@ -391,13 +381,11 @@ rte_atomic16_sub_return(rte_atomic16_t *v, int16_t
> dec)
> */
> static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
> {
> return rte_atomic_fetch_add_explicit((volatile __rte_atomic int16_t *)&v-
> >cnt, 1,
> rte_memory_order_seq_cst) + 1 == 0;
> }
> -#endif
>
> /**
> * Atomically decrement a 16-bit counter by one and test.
> @@ -412,13 +400,11 @@ static inline int
> rte_atomic16_inc_and_test(rte_atomic16_t *v)
> */
> static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
> {
> return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int16_t *)&v-
> >cnt, 1,
> rte_memory_order_seq_cst) - 1 == 0;
> }
> -#endif
>
> /**
> * Atomically test and set a 16-bit atomic counter.
> @@ -433,12 +419,10 @@ static inline int
> rte_atomic16_dec_and_test(rte_atomic16_t *v)
> */
> static inline int rte_atomic16_test_and_set(rte_atomic16_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
> {
> return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
> }
> -#endif
>
> /**
> * Atomically set a 16-bit counter to 0.
> @@ -472,13 +456,11 @@ static inline void rte_atomic16_clear(rte_atomic16_t
> *v)
> static inline int
> rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int
> rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
> {
> return __sync_bool_compare_and_swap(dst, exp, src);
> }
> -#endif
>
> /**
> * Atomic exchange.
> @@ -496,15 +478,11 @@ rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t
> exp, uint32_t src)
> * The original value at that location
> */
> static inline uint32_t
> -rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val);
> -
> -#ifdef RTE_FORCE_INTRINSICS
> -static inline uint32_t
> rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
> {
> - return rte_atomic_exchange_explicit(dst, val,
> rte_memory_order_seq_cst);
> + return rte_atomic_exchange_explicit((volatile __rte_atomic uint32_t
> *)dst,
> + val, rte_memory_order_seq_cst);
> }
> -#endif
>
> /**
> * The atomic counter structure.
> @@ -597,13 +575,11 @@ rte_atomic32_sub(rte_atomic32_t *v, int32_t dec)
> static inline void
> rte_atomic32_inc(rte_atomic32_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic32_inc(rte_atomic32_t *v)
> {
> rte_atomic32_add(v, 1);
> }
> -#endif
>
> /**
> * Atomically decrement a counter by one.
> @@ -614,13 +590,11 @@ rte_atomic32_inc(rte_atomic32_t *v)
> static inline void
> rte_atomic32_dec(rte_atomic32_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic32_dec(rte_atomic32_t *v)
> {
> rte_atomic32_sub(v,1);
> }
> -#endif
>
> /**
> * Atomically add a 32-bit value to a counter and return the result.
> @@ -676,13 +650,11 @@ rte_atomic32_sub_return(rte_atomic32_t *v, int32_t
> dec)
> */
> static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
> {
> return rte_atomic_fetch_add_explicit((volatile __rte_atomic int32_t *)&v-
> >cnt, 1,
> rte_memory_order_seq_cst) + 1 == 0;
> }
> -#endif
>
> /**
> * Atomically decrement a 32-bit counter by one and test.
> @@ -697,13 +669,11 @@ static inline int
> rte_atomic32_inc_and_test(rte_atomic32_t *v)
> */
> static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
> {
> return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int32_t *)&v-
> >cnt, 1,
> rte_memory_order_seq_cst) - 1 == 0;
> }
> -#endif
>
> /**
> * Atomically test and set a 32-bit atomic counter.
> @@ -718,12 +688,10 @@ static inline int
> rte_atomic32_dec_and_test(rte_atomic32_t *v)
> */
> static inline int rte_atomic32_test_and_set(rte_atomic32_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
> {
> return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
> }
> -#endif
>
> /**
> * Atomically set a 32-bit counter to 0.
> @@ -756,13 +724,11 @@ static inline void rte_atomic32_clear(rte_atomic32_t
> *v)
> static inline int
> rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int
> rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
> {
> return __sync_bool_compare_and_swap(dst, exp, src);
> }
> -#endif
>
> /**
> * Atomic exchange.
> @@ -780,15 +746,11 @@ rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t
> exp, uint64_t src)
> * The original value at that location
> */
> static inline uint64_t
> -rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val);
> -
> -#ifdef RTE_FORCE_INTRINSICS
> -static inline uint64_t
> rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
> {
> - return rte_atomic_exchange_explicit(dst, val,
> rte_memory_order_seq_cst);
> + return rte_atomic_exchange_explicit((volatile __rte_atomic uint64_t
> *)dst,
> + val, rte_memory_order_seq_cst);
> }
> -#endif
>
> /**
> * The atomic counter structure.
> @@ -811,7 +773,6 @@ typedef struct {
> static inline void
> rte_atomic64_init(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic64_init(rte_atomic64_t *v)
> {
> @@ -828,7 +789,6 @@ rte_atomic64_init(rte_atomic64_t *v)
> }
> #endif
> }
> -#endif
>
> /**
> * Atomically read a 64-bit counter.
> @@ -841,7 +801,6 @@ rte_atomic64_init(rte_atomic64_t *v)
> static inline int64_t
> rte_atomic64_read(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int64_t
> rte_atomic64_read(rte_atomic64_t *v)
> {
> @@ -860,7 +819,6 @@ rte_atomic64_read(rte_atomic64_t *v)
> return tmp;
> #endif
> }
> -#endif
>
> /**
> * Atomically set a 64-bit counter.
> @@ -873,7 +831,6 @@ rte_atomic64_read(rte_atomic64_t *v)
> static inline void
> rte_atomic64_set(rte_atomic64_t *v, int64_t new_value);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
> {
> @@ -890,7 +847,6 @@ rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
> }
> #endif
> }
> -#endif
>
> /**
> * Atomically add a 64-bit value to a counter.
> @@ -903,14 +859,12 @@ rte_atomic64_set(rte_atomic64_t *v, int64_t
> new_value)
> static inline void
> rte_atomic64_add(rte_atomic64_t *v, int64_t inc);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
> {
> rte_atomic_fetch_add_explicit((volatile __rte_atomic int64_t *)&v->cnt,
> inc,
> rte_memory_order_seq_cst);
> }
> -#endif
>
> /**
> * Atomically subtract a 64-bit value from a counter.
> @@ -923,14 +877,12 @@ rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
> static inline void
> rte_atomic64_sub(rte_atomic64_t *v, int64_t dec);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
> {
> rte_atomic_fetch_sub_explicit((volatile __rte_atomic int64_t *)&v->cnt,
> dec,
> rte_memory_order_seq_cst);
> }
> -#endif
>
> /**
> * Atomically increment a 64-bit counter by one and test.
> @@ -941,13 +893,11 @@ rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
> static inline void
> rte_atomic64_inc(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic64_inc(rte_atomic64_t *v)
> {
> rte_atomic64_add(v, 1);
> }
> -#endif
>
> /**
> * Atomically decrement a 64-bit counter by one and test.
> @@ -958,13 +908,11 @@ rte_atomic64_inc(rte_atomic64_t *v)
> static inline void
> rte_atomic64_dec(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void
> rte_atomic64_dec(rte_atomic64_t *v)
> {
> rte_atomic64_sub(v, 1);
> }
> -#endif
>
> /**
> * Add a 64-bit value to an atomic counter and return the result.
> @@ -982,14 +930,12 @@ rte_atomic64_dec(rte_atomic64_t *v)
> static inline int64_t
> rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int64_t
> rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
> {
> return rte_atomic_fetch_add_explicit((volatile __rte_atomic int64_t *)&v-
> >cnt, inc,
> rte_memory_order_seq_cst) + inc;
> }
> -#endif
>
> /**
> * Subtract a 64-bit value from an atomic counter and return the result.
> @@ -1007,14 +953,12 @@ rte_atomic64_add_return(rte_atomic64_t *v, int64_t
> inc)
> static inline int64_t
> rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int64_t
> rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
> {
> return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int64_t *)&v-
> >cnt, dec,
> rte_memory_order_seq_cst) - dec;
> }
> -#endif
>
> /**
> * Atomically increment a 64-bit counter by one and test.
> @@ -1029,12 +973,10 @@ rte_atomic64_sub_return(rte_atomic64_t *v, int64_t
> dec)
> */
> static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
> {
> return rte_atomic64_add_return(v, 1) == 0;
> }
> -#endif
>
> /**
> * Atomically decrement a 64-bit counter by one and test.
> @@ -1049,12 +991,10 @@ static inline int
> rte_atomic64_inc_and_test(rte_atomic64_t *v)
> */
> static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
> {
> return rte_atomic64_sub_return(v, 1) == 0;
> }
> -#endif
>
> /**
> * Atomically test and set a 64-bit atomic counter.
> @@ -1069,12 +1009,10 @@ static inline int
> rte_atomic64_dec_and_test(rte_atomic64_t *v)
> */
> static inline int rte_atomic64_test_and_set(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
> {
> return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
> }
> -#endif
>
> /**
> * Atomically set a 64-bit counter to 0.
> @@ -1084,12 +1022,10 @@ static inline int
> rte_atomic64_test_and_set(rte_atomic64_t *v)
> */
> static inline void rte_atomic64_clear(rte_atomic64_t *v);
>
> -#ifdef RTE_FORCE_INTRINSICS
> static inline void rte_atomic64_clear(rte_atomic64_t *v)
> {
> rte_atomic64_set(v, 0);
> }
> -#endif
>
> #endif
>
> diff --git a/lib/eal/loongarch/include/rte_atomic.h
> b/lib/eal/loongarch/include/rte_atomic.h
> index c8066a4612..785a452c9e 100644
> --- a/lib/eal/loongarch/include/rte_atomic.h
> +++ b/lib/eal/loongarch/include/rte_atomic.h
> @@ -5,10 +5,6 @@
> #ifndef RTE_ATOMIC_LOONGARCH_H
> #define RTE_ATOMIC_LOONGARCH_H
>
> -#ifndef RTE_FORCE_INTRINSICS
> -# error Platform must be built with RTE_FORCE_INTRINSICS
> -#endif
> -
> #include <rte_common.h>
> #include "generic/rte_atomic.h"
>
> diff --git a/lib/eal/ppc/include/rte_atomic.h b/lib/eal/ppc/include/rte_atomic.h
> index 10acc238f9..64f4c3d670 100644
> --- a/lib/eal/ppc/include/rte_atomic.h
> +++ b/lib/eal/ppc/include/rte_atomic.h
> @@ -43,179 +43,6 @@ rte_atomic_thread_fence(rte_memory_order memorder)
> }
>
> /*------------------------- 16 bit atomic operations -------------------------*/
> -#ifndef RTE_FORCE_INTRINSICS
> -static inline int
> -rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
> -{
> - return rte_atomic_compare_exchange_strong_explicit(dst, &exp, src,
> rte_memory_order_acquire,
> - rte_memory_order_acquire) ? 1 : 0;
> -}
> -
> -static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
> -{
> - return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
> -}
> -
> -static inline void
> -rte_atomic16_inc(rte_atomic16_t *v)
> -{
> - rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire);
> -}
> -
> -static inline void
> -rte_atomic16_dec(rte_atomic16_t *v)
> -{
> - rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire);
> -}
> -
> -static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
> -{
> - return rte_atomic_fetch_add_explicit(&v->cnt, 1,
> rte_memory_order_acquire) + 1 == 0;
> -}
> -
> -static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
> -{
> - return rte_atomic_fetch_sub_explicit(&v->cnt, 1,
> rte_memory_order_acquire) - 1 == 0;
> -}
> -
> -static inline uint16_t
> -rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
> -{
> - return __atomic_exchange_2(dst, val, rte_memory_order_seq_cst);
> -}
> -
> -/*------------------------- 32 bit atomic operations -------------------------*/
> -
> -static inline int
> -rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
> -{
> - return rte_atomic_compare_exchange_strong_explicit(dst, &exp, src,
> rte_memory_order_acquire,
> - rte_memory_order_acquire) ? 1 : 0;
> -}
> -
> -static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
> -{
> - return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
> -}
> -
> -static inline void
> -rte_atomic32_inc(rte_atomic32_t *v)
> -{
> - rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire);
> -}
> -
> -static inline void
> -rte_atomic32_dec(rte_atomic32_t *v)
> -{
> - rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire);
> -}
> -
> -static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
> -{
> - return rte_atomic_fetch_add_explicit(&v->cnt, 1,
> rte_memory_order_acquire) + 1 == 0;
> -}
> -
> -static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
> -{
> - return rte_atomic_fetch_sub_explicit(&v->cnt, 1,
> rte_memory_order_acquire) - 1 == 0;
> -}
> -
> -static inline uint32_t
> -rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
> -{
> - return __atomic_exchange_4(dst, val, rte_memory_order_seq_cst);
> -}
> -
> -/*------------------------- 64 bit atomic operations -------------------------*/
> -
> -static inline int
> -rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
> -{
> - return rte_atomic_compare_exchange_strong_explicit(dst, &exp, src,
> rte_memory_order_acquire,
> - rte_memory_order_acquire) ? 1 : 0;
> -}
> -
> -static inline void
> -rte_atomic64_init(rte_atomic64_t *v)
> -{
> - v->cnt = 0;
> -}
> -
> -static inline int64_t
> -rte_atomic64_read(rte_atomic64_t *v)
> -{
> - return v->cnt;
> -}
> -
> -static inline void
> -rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
> -{
> - v->cnt = new_value;
> -}
> -
> -static inline void
> -rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
> -{
> - rte_atomic_fetch_add_explicit(&v->cnt, inc, rte_memory_order_acquire);
> -}
> -
> -static inline void
> -rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
> -{
> - rte_atomic_fetch_sub_explicit(&v->cnt, dec,
> rte_memory_order_acquire);
> -}
> -
> -static inline void
> -rte_atomic64_inc(rte_atomic64_t *v)
> -{
> - rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire);
> -}
> -
> -static inline void
> -rte_atomic64_dec(rte_atomic64_t *v)
> -{
> - rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire);
> -}
> -
> -static inline int64_t
> -rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
> -{
> - return rte_atomic_fetch_add_explicit(&v->cnt, inc,
> rte_memory_order_acquire) + inc;
> -}
> -
> -static inline int64_t
> -rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
> -{
> - return rte_atomic_fetch_sub_explicit(&v->cnt, dec,
> rte_memory_order_acquire) - dec;
> -}
> -
> -static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
> -{
> - return rte_atomic_fetch_add_explicit(&v->cnt, 1,
> rte_memory_order_acquire) + 1 == 0;
> -}
> -
> -static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
> -{
> - return rte_atomic_fetch_sub_explicit(&v->cnt, 1,
> rte_memory_order_acquire) - 1 == 0;
> -}
> -
> -static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
> -{
> - return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
> -}
> -
> -static inline void rte_atomic64_clear(rte_atomic64_t *v)
> -{
> - v->cnt = 0;
> -}
> -
> -static inline uint64_t
> -rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
> -{
> - return __atomic_exchange_8(dst, val, rte_memory_order_seq_cst);
> -}
> -
> -#endif
>
> #ifdef __cplusplus
> }
> diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h
> index 66346ad474..061b175f33 100644
> --- a/lib/eal/riscv/include/rte_atomic.h
> +++ b/lib/eal/riscv/include/rte_atomic.h
> @@ -8,10 +8,6 @@
> #ifndef RTE_ATOMIC_RISCV_H
> #define RTE_ATOMIC_RISCV_H
>
> -#ifndef RTE_FORCE_INTRINSICS
> -# error Platform must be built with RTE_FORCE_INTRINSICS
> -#endif
> -
> #include <stdint.h>
> #include <rte_common.h>
> #include <rte_config.h>
> diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h
> index e071e4234e..4f05302c9f 100644
> --- a/lib/eal/x86/include/rte_atomic.h
> +++ b/lib/eal/x86/include/rte_atomic.h
> @@ -111,178 +111,6 @@ rte_atomic_thread_fence(rte_memory_order
> memorder)
> extern "C" {
> #endif
>
> -#ifndef RTE_FORCE_INTRINSICS
> -static inline int
> -rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
> -{
> - uint8_t res;
> -
> - asm volatile(
> - MPLOCKED
> - "cmpxchgw %[src], %[dst];"
> - "sete %[res];"
> - : [res] "=a" (res), /* output */
> - [dst] "=m" (*dst)
> - : [src] "r" (src), /* input */
> - "a" (exp),
> - "m" (*dst)
> - : "memory"); /* no-clobber list */
> - return res;
> -}
> -
> -static inline uint16_t
> -rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
> -{
> - asm volatile(
> - MPLOCKED
> - "xchgw %0, %1;"
> - : "=r" (val), "=m" (*dst)
> - : "0" (val), "m" (*dst)
> - : "memory"); /* no-clobber list */
> - return val;
> -}
> -
> -static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
> -{
> - return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
> -}
> -
> -static inline void
> -rte_atomic16_inc(rte_atomic16_t *v)
> -{
> - asm volatile(
> - MPLOCKED
> - "incw %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : "m" (v->cnt) /* input */
> - );
> -}
> -
> -static inline void
> -rte_atomic16_dec(rte_atomic16_t *v)
> -{
> - asm volatile(
> - MPLOCKED
> - "decw %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : "m" (v->cnt) /* input */
> - );
> -}
> -
> -static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
> -{
> - uint8_t ret;
> -
> - asm volatile(
> - MPLOCKED
> - "incw %[cnt] ; "
> - "sete %[ret]"
> - : [cnt] "+m" (v->cnt), /* output */
> - [ret] "=qm" (ret)
> - );
> - return ret != 0;
> -}
> -
> -static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
> -{
> - uint8_t ret;
> -
> - asm volatile(MPLOCKED
> - "decw %[cnt] ; "
> - "sete %[ret]"
> - : [cnt] "+m" (v->cnt), /* output */
> - [ret] "=qm" (ret)
> - );
> - return ret != 0;
> -}
> -
> -/*------------------------- 32 bit atomic operations -------------------------*/
> -
> -static inline int
> -rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
> -{
> - uint8_t res;
> -
> - asm volatile(
> - MPLOCKED
> - "cmpxchgl %[src], %[dst];"
> - "sete %[res];"
> - : [res] "=a" (res), /* output */
> - [dst] "=m" (*dst)
> - : [src] "r" (src), /* input */
> - "a" (exp),
> - "m" (*dst)
> - : "memory"); /* no-clobber list */
> - return res;
> -}
> -
> -static inline uint32_t
> -rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
> -{
> - asm volatile(
> - MPLOCKED
> - "xchgl %0, %1;"
> - : "=r" (val), "=m" (*dst)
> - : "0" (val), "m" (*dst)
> - : "memory"); /* no-clobber list */
> - return val;
> -}
> -
> -static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
> -{
> - return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
> -}
> -
> -static inline void
> -rte_atomic32_inc(rte_atomic32_t *v)
> -{
> - asm volatile(
> - MPLOCKED
> - "incl %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : "m" (v->cnt) /* input */
> - );
> -}
> -
> -static inline void
> -rte_atomic32_dec(rte_atomic32_t *v)
> -{
> - asm volatile(
> - MPLOCKED
> - "decl %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : "m" (v->cnt) /* input */
> - );
> -}
> -
> -static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
> -{
> - uint8_t ret;
> -
> - asm volatile(
> - MPLOCKED
> - "incl %[cnt] ; "
> - "sete %[ret]"
> - : [cnt] "+m" (v->cnt), /* output */
> - [ret] "=qm" (ret)
> - );
> - return ret != 0;
> -}
> -
> -static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
> -{
> - uint8_t ret;
> -
> - asm volatile(MPLOCKED
> - "decl %[cnt] ; "
> - "sete %[ret]"
> - : [cnt] "+m" (v->cnt), /* output */
> - [ret] "=qm" (ret)
> - );
> - return ret != 0;
> -}
> -
> -#endif /* !RTE_FORCE_INTRINSICS */
>
> #ifdef __cplusplus
> }
> diff --git a/lib/eal/x86/include/rte_atomic_32.h
> b/lib/eal/x86/include/rte_atomic_32.h
> index 0f25863aa5..37d139f30d 100644
> --- a/lib/eal/x86/include/rte_atomic_32.h
> +++ b/lib/eal/x86/include/rte_atomic_32.h
> @@ -20,193 +20,5 @@
>
> /*------------------------- 64 bit atomic operations -------------------------*/
>
> -#ifndef RTE_FORCE_INTRINSICS
> -static inline int
> -rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
> -{
> - uint8_t res;
> - union {
> - struct {
> - uint32_t l32;
> - uint32_t h32;
> - };
> - uint64_t u64;
> - } _exp, _src;
> -
> - _exp.u64 = exp;
> - _src.u64 = src;
> -
> -#ifndef __PIC__
> - asm volatile (
> - MPLOCKED
> - "cmpxchg8b (%[dst]);"
> - "setz %[res];"
> - : [res] "=a" (res) /* result in eax */
> - : [dst] "S" (dst), /* esi */
> - "b" (_src.l32), /* ebx */
> - "c" (_src.h32), /* ecx */
> - "a" (_exp.l32), /* eax */
> - "d" (_exp.h32) /* edx */
> - : "memory" ); /* no-clobber list */
> -#else
> - asm volatile (
> - "xchgl %%ebx, %%edi;\n"
> - MPLOCKED
> - "cmpxchg8b (%[dst]);"
> - "setz %[res];"
> - "xchgl %%ebx, %%edi;\n"
> - : [res] "=a" (res) /* result in eax */
> - : [dst] "S" (dst), /* esi */
> - "D" (_src.l32), /* ebx */
> - "c" (_src.h32), /* ecx */
> - "a" (_exp.l32), /* eax */
> - "d" (_exp.h32) /* edx */
> - : "memory" ); /* no-clobber list */
> -#endif
> -
> - return res;
> -}
> -
> -static inline uint64_t
> -rte_atomic64_exchange(volatile uint64_t *dest, uint64_t val)
> -{
> - uint64_t old;
> -
> - do {
> - old = *dest;
> - } while (rte_atomic64_cmpset(dest, old, val) == 0);
> -
> - return old;
> -}
> -
> -static inline void
> -rte_atomic64_init(rte_atomic64_t *v)
> -{
> - int success = 0;
> - uint64_t tmp;
> -
> - while (success == 0) {
> - tmp = v->cnt;
> - success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
> - tmp, 0);
> - }
> -}
> -
> -static inline int64_t
> -rte_atomic64_read(rte_atomic64_t *v)
> -{
> - int success = 0;
> - uint64_t tmp;
> -
> - while (success == 0) {
> - tmp = v->cnt;
> - /* replace the value by itself */
> - success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
> - tmp, tmp);
> - }
> - return tmp;
> -}
> -
> -static inline void
> -rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
> -{
> - int success = 0;
> - uint64_t tmp;
> -
> - while (success == 0) {
> - tmp = v->cnt;
> - success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
> - tmp, new_value);
> - }
> -}
> -
> -static inline void
> -rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
> -{
> - int success = 0;
> - uint64_t tmp;
> -
> - while (success == 0) {
> - tmp = v->cnt;
> - success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
> - tmp, tmp + inc);
> - }
> -}
> -
> -static inline void
> -rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
> -{
> - int success = 0;
> - uint64_t tmp;
> -
> - while (success == 0) {
> - tmp = v->cnt;
> - success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
> - tmp, tmp - dec);
> - }
> -}
> -
> -static inline void
> -rte_atomic64_inc(rte_atomic64_t *v)
> -{
> - rte_atomic64_add(v, 1);
> -}
> -
> -static inline void
> -rte_atomic64_dec(rte_atomic64_t *v)
> -{
> - rte_atomic64_sub(v, 1);
> -}
> -
> -static inline int64_t
> -rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
> -{
> - int success = 0;
> - uint64_t tmp;
> -
> - while (success == 0) {
> - tmp = v->cnt;
> - success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
> - tmp, tmp + inc);
> - }
> -
> - return tmp + inc;
> -}
> -
> -static inline int64_t
> -rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
> -{
> - int success = 0;
> - uint64_t tmp;
> -
> - while (success == 0) {
> - tmp = v->cnt;
> - success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
> - tmp, tmp - dec);
> - }
> -
> - return tmp - dec;
> -}
> -
> -static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
> -{
> - return rte_atomic64_add_return(v, 1) == 0;
> -}
> -
> -static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
> -{
> - return rte_atomic64_sub_return(v, 1) == 0;
> -}
> -
> -static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
> -{
> - return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
> -}
> -
> -static inline void rte_atomic64_clear(rte_atomic64_t *v)
> -{
> - rte_atomic64_set(v, 0);
> -}
> -#endif
>
> #endif /* _RTE_ATOMIC_I686_H_ */
> diff --git a/lib/eal/x86/include/rte_atomic_64.h
> b/lib/eal/x86/include/rte_atomic_64.h
> index 0a7a2131e0..1cd12695a2 100644
> --- a/lib/eal/x86/include/rte_atomic_64.h
> +++ b/lib/eal/x86/include/rte_atomic_64.h
> @@ -22,163 +22,6 @@
>
> /*------------------------- 64 bit atomic operations -------------------------*/
>
> -#ifndef RTE_FORCE_INTRINSICS
> -static inline int
> -rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
> -{
> - uint8_t res;
> -
> -
> - asm volatile(
> - MPLOCKED
> - "cmpxchgq %[src], %[dst];"
> - "sete %[res];"
> - : [res] "=a" (res), /* output */
> - [dst] "=m" (*dst)
> - : [src] "r" (src), /* input */
> - "a" (exp),
> - "m" (*dst)
> - : "memory"); /* no-clobber list */
> -
> - return res;
> -}
> -
> -static inline uint64_t
> -rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
> -{
> - asm volatile(
> - MPLOCKED
> - "xchgq %0, %1;"
> - : "=r" (val), "=m" (*dst)
> - : "0" (val), "m" (*dst)
> - : "memory"); /* no-clobber list */
> - return val;
> -}
> -
> -static inline void
> -rte_atomic64_init(rte_atomic64_t *v)
> -{
> - v->cnt = 0;
> -}
> -
> -static inline int64_t
> -rte_atomic64_read(rte_atomic64_t *v)
> -{
> - return v->cnt;
> -}
> -
> -static inline void
> -rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
> -{
> - v->cnt = new_value;
> -}
> -
> -static inline void
> -rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
> -{
> - asm volatile(
> - MPLOCKED
> - "addq %[inc], %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : [inc] "ir" (inc), /* input */
> - "m" (v->cnt)
> - );
> -}
> -
> -static inline void
> -rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
> -{
> - asm volatile(
> - MPLOCKED
> - "subq %[dec], %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : [dec] "ir" (dec), /* input */
> - "m" (v->cnt)
> - );
> -}
> -
> -static inline void
> -rte_atomic64_inc(rte_atomic64_t *v)
> -{
> - asm volatile(
> - MPLOCKED
> - "incq %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : "m" (v->cnt) /* input */
> - );
> -}
> -
> -static inline void
> -rte_atomic64_dec(rte_atomic64_t *v)
> -{
> - asm volatile(
> - MPLOCKED
> - "decq %[cnt]"
> - : [cnt] "=m" (v->cnt) /* output */
> - : "m" (v->cnt) /* input */
> - );
> -}
> -
> -static inline int64_t
> -rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
> -{
> - int64_t prev = inc;
> -
> - asm volatile(
> - MPLOCKED
> - "xaddq %[prev], %[cnt]"
> - : [prev] "+r" (prev), /* output */
> - [cnt] "=m" (v->cnt)
> - : "m" (v->cnt) /* input */
> - );
> - return prev + inc;
> -}
> -
> -static inline int64_t
> -rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
> -{
> - return rte_atomic64_add_return(v, -dec);
> -}
> -
> -static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
> -{
> - uint8_t ret;
> -
> - asm volatile(
> - MPLOCKED
> - "incq %[cnt] ; "
> - "sete %[ret]"
> - : [cnt] "+m" (v->cnt), /* output */
> - [ret] "=qm" (ret)
> - );
> -
> - return ret != 0;
> -}
> -
> -static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
> -{
> - uint8_t ret;
> -
> - asm volatile(
> - MPLOCKED
> - "decq %[cnt] ; "
> - "sete %[ret]"
> - : [cnt] "+m" (v->cnt), /* output */
> - [ret] "=qm" (ret)
> - );
> - return ret != 0;
> -}
> -
> -static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
> -{
> - return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
> -}
> -
> -static inline void rte_atomic64_clear(rte_atomic64_t *v)
> -{
> - v->cnt = 0;
> -}
> -#endif
>
> /*------------------------ 128 bit atomic operations -------------------------*/
>
> --
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
> 2.53.0
next prev parent reply other threads:[~2026-06-01 18:23 UTC|newest]
Thread overview: 105+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-21 4:17 [RFC 0/7] prepare deprecation of rte_atomicNN_*() family Stephen Hemminger
2026-05-21 4:17 ` [RFC 1/7] doc: update versions in deprecation file Stephen Hemminger
2026-05-21 4:17 ` [RFC 2/7] eal: reimplement rte_smp_*mb with rte_atomic_thread_fence Stephen Hemminger
2026-05-21 15:43 ` Wathsala Vithanage
2026-05-21 4:17 ` [RFC 3/7] ring: use C11 atomic operations for MP/SP head/tail Stephen Hemminger
2026-05-21 15:57 ` Wathsala Vithanage
2026-05-21 4:17 ` [RFC 4/7] net/zxdh: work around GCC bitfield uninit false positive Stephen Hemminger
2026-05-21 4:17 ` [RFC 5/7] net/bonding: use stdatomic Stephen Hemminger
2026-05-21 4:17 ` [RFC 6/7] net/nbl: remove unused rte_atomic16 field Stephen Hemminger
2026-05-21 4:17 ` [RFC 7/7] config: use RTE_FORCE_INTRINSICS on all platforms Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 00/11] prepare deprecation of rte_atomicNN_*() family Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 01/11] eal: use intrinsics for rte_atomic on all platforms Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 02/11] eal: reimplement rte_smp_*mb with rte_atomic_thread_fence Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 03/11] ring: use C11 atomic operations for MP/SP head/tail Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 04/11] net/bonding: use stdatomic Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 05/11] net/nbl: remove unused rte_atomic16 field Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 06/11] net/ena: replace use of rte_atomicNN Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 07/11] net/failsafe: convert to stdatomic Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 08/11] net/enic: do not use deprecated rte_atomic64 Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 09/11] net/pfe: use ethdev linkstatus helpers Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 10/11] net/sfc: replace rte_atomic with stdatomic Stephen Hemminger
2026-05-21 18:04 ` [RFC v2 11/11] crypto/ccp: replace use of rte_atomic64 " Stephen Hemminger
2026-05-22 14:19 ` [RFC v2 00/11] prepare deprecation of rte_atomicNN_*() family Bruce Richardson
2026-05-22 14:45 ` Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 00/27] deprecate rte_atomicNN family Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 01/27] eal: use intrinsics for rte_atomic on all platforms Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 02/27] eal: reimplement rte_smp_*mb with rte_atomic_thread_fence Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 03/27] ring: use compare-and-swap wrapper Stephen Hemminger
2026-05-25 7:41 ` Konstantin Ananyev
2026-05-25 14:31 ` Stephen Hemminger
2026-05-25 15:35 ` Stephen Hemminger
2026-05-25 15:47 ` Morten Brørup
2026-05-23 19:16 ` [PATCH v3 04/27] bpf: replace atomic op macro with typed helpers Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 05/27] net/bonding: use stdatomic Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 06/27] net/nbl: remove unused rte_atomic16 field Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 07/27] net/ena: replace use of rte_atomicNN Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 08/27] net/failsafe: convert to stdatomic Stephen Hemminger
2026-05-23 19:16 ` [PATCH v3 09/27] net/enic: do not use deprecated rte_atomic64 Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 00/27] deprecate rte_atomicNN family Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 01/27] eal: use intrinsics for rte_atomic on all platforms Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 02/27] eal: reimplement rte_smp_*mb with rte_atomic_thread_fence Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 03/27] ring: use compare-and-swap wrapper Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 04/27] bpf: replace atomic op macro with typed helpers Stephen Hemminger
2026-05-25 10:49 ` Marat Khalili
2026-05-23 19:56 ` [PATCH v3 05/27] net/bonding: use stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 06/27] net/nbl: remove unused rte_atomic16 field Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 07/27] net/ena: replace use of rte_atomicNN Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 08/27] net/failsafe: convert to stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 09/27] net/enic: do not use deprecated rte_atomic64 Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 10/27] net/pfe: use ethdev linkstatus helpers Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 11/27] net/sfc: replace rte_atomic with stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 12/27] crypto/ccp: replace use of rte_atomic64 " Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 13/27] bus/dpaa: replace rte_atomic16 " Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 14/27] drivers: " Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 15/27] net/netvsc: replace rte_atomic32 " Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 16/27] event/sw: convert from rte_atomic32 to stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 17/27] bus/vmbus: convert from rte_atomic " Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 18/27] common/dpaax: remove unused atomic macros Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 19/27] net/bnx2x: convert from rte_atomic32 to stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 20/27] bus/fslmc: replace rte_atomic32 with stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 21/27] drivers/event: replace rte_atomic32 in selftests Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 22/27] net/hinic: replace rte_atomic32 with stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 23/27] net/txgbe: " Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 24/27] net/vhost: use stdatomic instead of rte_atomic32 Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 25/27] vdpa/ifc: replace rte_atomic32 with stdatomic Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 26/27] test/atomic: suppress deprecation warnings for legacy APIs Stephen Hemminger
2026-05-23 19:56 ` [PATCH v3 27/27] eal: mark rte_atomicNN as deprecated Stephen Hemminger
2026-05-26 23:23 ` [PATCH v4 00/27] deprecate rte_atomicNN family Stephen Hemminger
2026-05-26 23:23 ` [PATCH v4 01/27] eal: use intrinsics for rte_atomic on all platforms Stephen Hemminger
2026-06-01 18:23 ` Konstantin Ananyev [this message]
2026-05-26 23:23 ` [PATCH v4 02/27] eal: reimplement rte_smp_*mb with rte_atomic_thread_fence Stephen Hemminger
2026-06-01 18:24 ` Konstantin Ananyev
2026-05-26 23:23 ` [PATCH v4 03/27] ring: unify memory model on C11, remove atomic32 Stephen Hemminger
2026-06-01 18:18 ` Konstantin Ananyev
2026-06-01 21:05 ` Stephen Hemminger
2026-06-01 21:18 ` Stephen Hemminger
2026-06-01 22:07 ` Stephen Hemminger
2026-05-26 23:23 ` [PATCH v4 04/27] bpf: use C11 atomics in BPF_ST_ATOMIC_REG Stephen Hemminger
2026-05-27 16:52 ` Marat Khalili
2026-05-26 23:23 ` [PATCH v4 05/27] net/bonding: use stdatomic Stephen Hemminger
2026-05-26 23:23 ` [PATCH v4 06/27] net/nbl: remove unused rte_atomic16 field Stephen Hemminger
2026-05-26 23:23 ` [PATCH v4 07/27] net/ena: replace use of rte_atomicNN Stephen Hemminger
2026-05-26 23:23 ` [PATCH v4 08/27] net/failsafe: convert to stdatomic Stephen Hemminger
2026-05-26 23:23 ` [PATCH v4 09/27] net/enic: do not use deprecated rte_atomic64 Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 10/27] net/pfe: use ethdev linkstatus helpers Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 11/27] net/sfc: replace rte_atomic with stdatomic Stephen Hemminger
2026-06-01 9:22 ` Andrew Rybchenko
2026-05-26 23:24 ` [PATCH v4 12/27] crypto/ccp: replace use of rte_atomic64 " Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 13/27] bus/dpaa: replace rte_atomic16 " Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 14/27] drivers: " Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 15/27] net/netvsc: replace rte_atomic32 " Stephen Hemminger
2026-05-27 0:29 ` [EXTERNAL] " Long Li
2026-05-31 16:35 ` Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 16/27] event/sw: convert from rte_atomic32 to stdatomic Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 17/27] bus/vmbus: convert from rte_atomic " Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 18/27] common/dpaax: use stdatomic instead of rte_atomic Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 19/27] net/bnx2x: convert from rte_atomic32 to stdatomic Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 20/27] bus/fslmc: replace rte_atomic32 with stdatomic Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 21/27] drivers/event: replace rte_atomic32 in selftests Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 22/27] net/hinic: replace rte_atomic32 with stdatomic Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 23/27] net/txgbe: " Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 24/27] net/vhost: use stdatomic instead of rte_atomic32 Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 25/27] vdpa/ifc: replace rte_atomic32 with stdatomic Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 26/27] test/atomic: suppress deprecation warnings for legacy APIs Stephen Hemminger
2026-05-26 23:24 ` [PATCH v4 27/27] eal: mark rte_atomicNN as deprecated Stephen Hemminger
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