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Thu, 20 Aug 2026 15:15:30 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4g354ypyp9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Aug 2026 15:15:30 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (smtpav06.dal12v.mail.ibm.com [10.241.53.105]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67KFFRgD60752324 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 20 Aug 2026 15:15:27 GMT Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8CAAF58059; Thu, 20 Aug 2026 15:15:27 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BA87058043; Thu, 20 Aug 2026 15:15:26 +0000 (GMT) Received: from mambor8.rchland.ibm.com (unknown [9.10.239.198]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 20 Aug 2026 15:15:26 +0000 (GMT) Message-ID: <3fea696f5ee62656ecca7aa72118da1d458a6018.camel@linux.ibm.com> Subject: Re: [PATCH 19/29] target/ppc: Refactor sleep and its variants to use a common helper From: Miles Glenn To: Chinmay Rath , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com Date: Thu, 20 Aug 2026 10:15:26 -0500 In-Reply-To: <20260820140114.327023-20-rathc@linux.ibm.com> References: <20260820140114.327023-1-rathc@linux.ibm.com> <20260820140114.327023-20-rathc@linux.ibm.com> Organization: IBM Content-Type: text/plain; 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envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Chinmay, This commit seems out of the scope of moving instructions to decodetree. Was this change necessary in order to move the instructions to decodetree? If so, it would be helpful to add that to the commit message. Otherwise, I would submit this separately from the decodetree commits. Thanks, Glenn On Thu, 2026-08-20 at 19:30 +0530, Chinmay Rath wrote: > From: Ojaswin Mujoo > > Refactor sleep, doze, nap, rvwinkle and stop to use a common helper > since they share majority of the code. Also refactor gen_hlper_pminsn() > to gen_helper_PMINSN() > > Signed-off-by: Ojaswin Mujoo > Signed-off-by: Chinmay Rath > --- > target/ppc/helper.h | 2 +- > target/ppc/tcg-excp_helper.c | 2 +- > .../ppc/translate/processor-ctrl-impl.c.inc | 99 +++---------------- > 3 files changed, 16 insertions(+), 87 deletions(-) > > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index cd2a0948a3..7e15676122 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -18,7 +18,7 @@ DEF_HELPER_1(rfdi, void, env) > DEF_HELPER_1(rfmci, void, env) > #if defined(TARGET_PPC64) > DEF_HELPER_2(scv, noreturn, env, i32) > -DEF_HELPER_2(pminsn, void, env, i32) > +DEF_HELPER_2(PMINSN, void, env, i32) > DEF_HELPER_1(rfid, void, env) > DEF_HELPER_1(rfscv, void, env) > DEF_HELPER_1(hrfid, void, env) > diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c > index b04f07a637..c4ffa2dfbb 100644 > --- a/target/ppc/tcg-excp_helper.c > +++ b/target/ppc/tcg-excp_helper.c > @@ -459,7 +459,7 @@ void helper_scv(CPUPPCState *env, uint32_t lev) > } > } > > -void helper_pminsn(CPUPPCState *env, uint32_t insn) > +void helper_PMINSN(CPUPPCState *env, uint32_t insn) > { > CPUState *cs = env_cpu(env); > > diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/translate/processor-ctrl-impl.c.inc > index bdbc195294..3b3ed3019a 100644 > --- a/target/ppc/translate/processor-ctrl-impl.c.inc > +++ b/target/ppc/translate/processor-ctrl-impl.c.inc > @@ -104,103 +104,32 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGSYNC *a) > return true; > } > > -static bool do_doze(DisasContext *ctx, arg_DOZE *a) > -{ > - REQUIRE_64BIT(ctx); > - > -#if defined(CONFIG_USER_ONLY) > - gen_priv_opc(ctx); > -#else > - TCGv_i32 t; > - > - REQUIRE_HV(ctx); > - translator_io_start(&ctx->base); > - t = tcg_constant_i32(PPC_PM_DOZE); > - gen_helper_pminsn(tcg_env, t); > - /* Stop translation, as the CPU is supposed to sleep from now */ > - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); > -#endif /* defined(CONFIG_USER_ONLY) */ > - > - return true; > -} > -TRANS_FLAGS2(PM_ISA206, DOZE, do_doze); > - > -static bool do_nap(DisasContext *ctx, arg_NAP *a) > -{ > - REQUIRE_64BIT(ctx); > - > -#if defined(CONFIG_USER_ONLY) > - gen_priv_opc(ctx); > -#else > - TCGv_i32 t; > - > - REQUIRE_HV(ctx); > - translator_io_start(&ctx->base); > - t = tcg_constant_i32(PPC_PM_NAP); > - gen_helper_pminsn(tcg_env, t); > - /* Stop translation, as the CPU is supposed to sleep from now */ > - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); > -#endif /* defined(CONFIG_USER_ONLY) */ > - return true; > -} > -TRANS_FLAGS2(PM_ISA206, NAP, do_nap); > - > -static bool do_sleep(DisasContext *ctx, arg_SLEEP *a) > -{ > - REQUIRE_64BIT(ctx); > - > -#if defined(CONFIG_USER_ONLY) > - gen_priv_opc(ctx); > -#else > - TCGv_i32 t; > - > - REQUIRE_HV(ctx); > - translator_io_start(&ctx->base); > - t = tcg_constant_i32(PPC_PM_SLEEP); > - gen_helper_pminsn(tcg_env, t); > - /* Stop translation, as the CPU is supposed to sleep from now */ > - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); > -#endif /* defined(CONFIG_USER_ONLY) */ > - return true; > -} > -TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep); > - > -static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a) > +/* > + * Helper to handle DOZE, NAP, SLEEP, RVWINKLE & STOP. Since none of them use > + * any arguments just use a placeholder arg_SLEEP. > + */ > +static bool do_sleep(DisasContext *ctx, arg_SLEEP *a, powerpc_pm_insn_t type) > { > REQUIRE_64BIT(ctx); > > #if defined(CONFIG_USER_ONLY) > gen_priv_opc(ctx); > -#else > +#elif defined(TARGET_PPC64) > TCGv_i32 t; > > REQUIRE_HV(ctx); > translator_io_start(&ctx->base); > - t = tcg_constant_i32(PPC_PM_RVWINKLE); > - gen_helper_pminsn(tcg_env, t); > + t = tcg_constant_i32(type); > + gen_helper_PMINSN(tcg_env, t); > /* Stop translation, as the CPU is supposed to sleep from now */ > gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); > -#endif /* defined(CONFIG_USER_ONLY) */ > - return true; > -} > -TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle); > - > -static bool do_stop(DisasContext *ctx, arg_STOP *a) > -{ > - REQUIRE_64BIT(ctx); > - > -#if defined(CONFIG_USER_ONLY) > - gen_priv_opc(ctx); > #else > - TCGv_i32 t; > - > - REQUIRE_HV(ctx); > - translator_io_start(&ctx->base); > - t = tcg_constant_i32(PPC_PM_STOP); > - gen_helper_pminsn(tcg_env, t); > - /* Stop translation, as the CPU is supposed to sleep from now */ > - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); > + qemu_build_not_reached(); > #endif > return true; > } > -TRANS_FLAGS2(ISA300, STOP, do_stop); > +TRANS_FLAGS2(PM_ISA206, DOZE, do_sleep, PPC_PM_DOZE); > +TRANS_FLAGS2(PM_ISA206, NAP, do_sleep, PPC_PM_NAP); > +TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep, PPC_PM_SLEEP); > +TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_sleep, PPC_PM_RVWINKLE); > +TRANS_FLAGS2(ISA300, STOP, do_sleep, PPC_PM_STOP);