From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Nicholas Piggin <npiggin@gmail.com>, linuxppc-dev@lists.ozlabs.org
Cc: Anton Blanchard <anton@samba.org>, Nicholas Piggin <npiggin@gmail.com>
Subject: Re: powerpc/64s: reduce exception alignment
Date: Mon, 14 Nov 2016 23:17:23 +1100 (AEDT) [thread overview]
Message-ID: <3tHTzl660gz9t2b@ozlabs.org> (raw)
In-Reply-To: <20161013034352.9410-1-npiggin@gmail.com>
On Thu, 2016-13-10 at 03:43:52 UTC, Nicholas Piggin wrote:
> Exception handlers are aligned to 128 bytes (L1 cache) on 64s, which is
> overkill. It can reduce the icache footprint of any individual exception
> path. However taken as a whole, the expansion in icache footprint seems
> likely to be counter-productive and cause more total misses.
>
> Create IFETCH_ALIGN_SHIFT/BYTES, which should give optimal ifetch
> alignment with much more reasonable alignment. This saves 1792 bytes
> from head_64.o text with an allmodconfig build.
>
> Other subarchitectures should define appropriate IFETCH_ALIGN_SHIFT
> values if this becomes more widely used.
>
> Cc: Anton Blanchard <anton@samba.org>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/f4329f2ecb149282fdfdd8830a936a
cheers
prev parent reply other threads:[~2016-11-14 12:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-13 3:43 [PATCH] powerpc/64s: reduce exception alignment Nicholas Piggin
2016-11-14 12:17 ` Michael Ellerman [this message]
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