From: "Mark A. Greer" <mgreer@mvista.com>
To: benh@kernel.crashing.org
Cc: debian-powerpc@lists.debian.org, debian-powerpc@lists.debian.org,
linuxppc-dev@lists.linuxppc.org
Subject: Re: Need testers: G3 @ G4 laptops (powerbooks & ibooks)
Date: Wed, 25 Feb 2004 14:46:07 -0700 [thread overview]
Message-ID: <403D179F.7040101@mvista.com> (raw)
>/ Are you sure that you can get away with this, passed on how the
manuals/
>/ (745x) describe the sequence of flush/invalidating the L2 (and,
L3) ?/
Do they describe disabling the L1 at all ?
[Somehow I was removed from the -dev & -embedded list. I was wondering
why I hadn't seen anything for a while :)]
[Also, trini prodded me to send this email and I didn't go back and read
the whole thread so this may be a little out of context]
Ben, FYI,
The latest 745x user manual is here:
http://e-www.motorola.com/files/32bit/doc/ref_manual/MPC7450UM.pdf
Here are some relevant sections:
- 3.4.1.1 (p. 3-32) Enabling and Disabling the Data Cache
- 3.4.1.3 (p. 3-33) Enabling and Disabling the Instruction Cache
- 3.6.3.1.5 (p. 3-55) Flushing of L1, L2, and L3
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next reply other threads:[~2004-02-25 21:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-02-25 21:46 Mark A. Greer [this message]
2004-02-25 23:47 ` Need testers: G3 @ G4 laptops (powerbooks & ibooks) Benjamin Herrenschmidt
-- strict thread matches above, loose matches on Subject: below --
2004-02-18 3:21 Benjamin Herrenschmidt
2004-02-18 15:45 ` Kiko Piris
2004-02-18 22:30 ` Benjamin Herrenschmidt
2004-02-18 16:03 ` digger vermont
2004-02-18 16:09 ` Colin Leroy
2004-02-18 16:31 ` digger vermont
2004-02-18 22:31 ` Benjamin Herrenschmidt
2004-02-18 17:45 ` Greg Watson
2004-02-18 17:58 ` digger vermont
2004-02-18 18:04 ` Michael Schmitz
2004-02-18 22:14 ` Ira Weiny
2004-02-24 17:54 ` Tom Rini
2004-02-24 22:39 ` Benjamin Herrenschmidt
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