From: Jan Beulich <jbeulich@suse.com>
To: "Sergii Dmytruk" <sergii.dmytruk@3mdeb.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger@xenproject.org>
Cc: Teddy Astie <teddy.astie@vates.tech>,
trenchboot-devel@googlegroups.com,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 01/23] x86/mtrr: get rid of a static variable on pause/restore
Date: Tue, 18 Aug 2026 13:44:05 +0200 [thread overview]
Message-ID: <403cc4a0-9b26-413d-bab8-03034e349c39@suse.com> (raw)
In-Reply-To: <b36573fda71fdceb3d6049493faf3daff9f64de8.1785668458.git.sergii.dmytruk@3mdeb.com>
On 02.08.2026 15:09, Sergii Dmytruk wrote:
> In addition to keeping the state in one place instead of on stack and in
> a static variable, this enables exposing this functionality to other
> units in the future.
>
> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
> ---
>
> Notes:
> v4: was called "x86/mtrr: expose functions for pausing caching"
> v4: no longer makes anything public, just updates implementation
> v4: the state structure is now an output parameter instead of a return value
I don't mind it to stay as you have it now, but recently we discussed this
aspect in another context, and I've changed my position: When the struct
can be returned in registers, it's okay to return by value.
> @@ -439,7 +440,7 @@ static DEFINE_SPINLOCK(set_atomicity_lock);
> * has been called.
> */
>
> -static bool prepare_set(void)
> +static void mtrr_pause_caching(struct mtrr_pausing_state *state)
> {
> unsigned long cr4;
Considering the conditional ...
> @@ -461,7 +462,9 @@ static bool prepare_set(void)
> alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP);
... cache flush that's done (and the comment just out of context also
correctly saying "no-fill cache mode"), we're not really pausing caching
in all cases. I'm therefore worried of the new names of the two involved
functions. Andrew, Roger - thoughts? (My inclination would be to suggest
mtrr_{pause,resume}_cache_fill().)
Jan
next prev parent reply other threads:[~2026-08-18 11:44 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-02 13:09 [PATCH v4 00/23] x86: Trenchboot Secure Launch DRTM (Xen) Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 01/23] x86/mtrr: get rid of a static variable on pause/restore Sergii Dmytruk
2026-08-18 11:44 ` Jan Beulich [this message]
2026-08-20 12:34 ` Teddy Astie
2026-08-02 13:09 ` [PATCH v4 02/23] x86/cpu: report SMX, TXT and SKINIT capabilities Sergii Dmytruk
2026-08-18 12:08 ` Jan Beulich
2026-08-20 13:14 ` Sergii Dmytruk
2026-08-20 15:48 ` Jan Beulich
2026-08-20 15:48 ` Andrew Cooper
2026-08-20 12:59 ` Teddy Astie
2026-08-20 15:09 ` Andrew Cooper
2026-08-02 13:09 ` [PATCH v4 03/23] x86/tpm.c: hashing and extending PCRs for TPM1.2 Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 04/23] x86/tpm.c: support extending PCRs of TPM2.0 via TIS Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 05/23] x86/tpm.c: add CRB interface support Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 06/23] x86/include/asm/intel-txt.h: constants and accessors for TXT registers and heap Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 07/23] x86/boot: add CONFIG_SLAUNCH, MLE header and Secure Launch entry point Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 08/23] include/xen/slr-table.h: Secure Launch Resource Table definitions Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 09/23] x86/boot/slaunch-early: implement early initialization Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 10/23] x86/boot/slaunch-early: early Intel TXT sanity checks Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 11/23] xen/arch/x86: reserve TXT memory during Slaunch Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 12/23] x86/slaunch: restore boot MTRRs after Intel TXT DRTM Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 13/23] x86/slaunch: measure MBI into TPM Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 14/23] x86/slaunch: update TPM event log (TPM1.2 or TPM2.0) Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 15/23] x86/hvm: check for VMX in SMX if Slaunch is active Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 16/23] x86/boot: choose AP stack based on APIC ID Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 17/23] x86/smpboot.c: TXT AP bringup Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 18/23] x86/slaunch: process DRTM policy Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 19/23] x86/acpi: disallow S3 on Secure Launch boot Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 20/23] x86/slaunch: support AMD CPUs Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 21/23] x86/slaunch: support EFI boot Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 22/23] xen/arch/x86: add TPR (TXT Protected Range) DMA protection support Sergii Dmytruk
2026-08-02 13:09 ` [PATCH v4 23/23] MAINTAINERS: add a section for TrenchBoot Slaunch Sergii Dmytruk
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=403cc4a0-9b26-413d-bab8-03034e349c39@suse.com \
--to=jbeulich@suse.com \
--cc=andrew.cooper3@citrix.com \
--cc=roger@xenproject.org \
--cc=sergii.dmytruk@3mdeb.com \
--cc=teddy.astie@vates.tech \
--cc=trenchboot-devel@googlegroups.com \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.