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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Cc: ravi.kumar.vodapalli@intel.com, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 14/14] drm/i915/mtl: Add multicast steering for media GT
Date: Mon, 3 Oct 2022 09:56:18 +0100	[thread overview]
Message-ID: <406ebfa6-b00c-b2ba-fd27-04e46de7ffc1@linux.intel.com> (raw)
In-Reply-To: <20221001004550.3031431-15-matthew.d.roper@intel.com>


Hi Matt,

On 01/10/2022 01:45, Matt Roper wrote:
> MTL's media GT only has a single type of steering ("OAADDRM") which
> selects between media slice 0 and media slice 1.  We'll always steer to
> media slice 0 unless it is fused off (which is the case when VD0, VE0,
> and SFC0 are all reported as unavailable).
> 
> Bspec: 67789
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c      | 19 +++++++++++++++++--
>   drivers/gpu/drm/i915/gt/intel_gt_types.h    |  1 +
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++++++++++-
>   3 files changed, 35 insertions(+), 3 deletions(-)

[snip]

> +static void
> +mtl_media_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> +{
> +	/*
> +	 * Unlike older platforms, we no longer setup implicit steering here;
> +	 * all MCR accesses are explicitly steered.
> +	 */
> +	if (drm_debug_enabled(DRM_UT_DRIVER)) {
> +		struct drm_printer p = drm_debug_printer("MCR Steering:");
> +
> +		intel_gt_mcr_report_steering(&p, gt, false);
> +	}
> +}
> +
>   static void
>   gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
>   {
>   	struct drm_i915_private *i915 = gt->i915;
>   
> -	if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
> +	if (IS_METEORLAKE(i915) && gt->type == GT_MEDIA)
> +		mtl_media_gt_workarounds_init(gt, wal);
> +	else if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
>   		mtl_3d_gt_workarounds_init(gt, wal);
>   	else if (IS_PONTEVECCHIO(i915))
>   		pvc_gt_workarounds_init(gt, wal);

Casually reading only - wouldn't it be nicer if the if-ladder in here 
(gt_init_workarounds) would have a single case per platform, and then 
you'd fork further (3d vs media) in MTL specific function?

Also, series ends up with mtl_media_gt_workarounds_init and 
mtl_3d_gt_workarounds_init apparently 100% identical. You will need two 
copies in the future?

Regards,

Tvrtko

  reply	other threads:[~2022-10-03  8:56 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-01  0:45 [Intel-gfx] [PATCH v2 00/14] Explicit MCR handling and MTL steering Matt Roper
2022-10-01  0:45 ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 01/14] drm/i915/gen8: Create separate reg definitions for new MCR registers Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 02/14] drm/i915/xehp: " Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 03/14] drm/i915/gt: Drop a few unused register definitions Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 04/14] drm/i915/gt: Correct prefix on a few registers Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 05/14] drm/i915/gt: Add intel_gt_mcr_multicast_rmw() operation Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 06/14] drm/i915/xehp: Check for faults on primary GAM Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 07/14] drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw() Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 08/14] drm/i915: Define MCR registers explicitly Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 09/14] drm/i915/gt: Always use MCR functions on multicast registers Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-12 16:18   ` [Intel-gfx] " Balasubramani Vivekanandan
2022-10-12 16:18     ` Balasubramani Vivekanandan
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 10/14] drm/i915/guc: Handle save/restore of MCR registers explicitly Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 11/14] drm/i915/gt: Add MCR-specific workaround initializers Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 12/14] drm/i915: Define multicast registers as a new type Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-04 12:56   ` [Intel-gfx] " Jani Nikula
2022-10-04 12:56     ` Jani Nikula
2022-10-04 13:00     ` [Intel-gfx] " Jani Nikula
2022-10-04 13:00       ` Jani Nikula
2022-10-05  1:01       ` [Intel-gfx] " Matt Roper
2022-10-05  1:01         ` Matt Roper
2022-10-13  7:21   ` [Intel-gfx] " Balasubramani Vivekanandan
2022-10-13  7:21     ` Balasubramani Vivekanandan
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 13/14] drm/i915/mtl: Add multicast steering for render GT Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-14 16:02   ` [Intel-gfx] " Balasubramani Vivekanandan
2022-10-14 16:02     ` Balasubramani Vivekanandan
2022-10-14 22:46     ` [Intel-gfx] " Matt Roper
2022-10-14 22:46       ` Matt Roper
2022-10-01  0:45 ` [Intel-gfx] [PATCH v2 14/14] drm/i915/mtl: Add multicast steering for media GT Matt Roper
2022-10-01  0:45   ` Matt Roper
2022-10-03  8:56   ` Tvrtko Ursulin [this message]
2022-10-03 19:32     ` [Intel-gfx] " Matt Roper
2022-10-04 10:13       ` Tvrtko Ursulin
2022-10-01  1:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev2) Patchwork
2022-10-01  1:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-01  2:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-01  5:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev3) Patchwork
2022-10-01  5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-01  5:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-01 21:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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