From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jeff Garzik Subject: Re: piix dma setup code Date: Wed, 19 May 2004 18:31:52 -0400 Sender: linux-ide-owner@vger.kernel.org Message-ID: <40ABE058.7070705@pobox.com> References: <40A9F150.4070209@turbolinux.co.jp> <200405191851.06281.bzolnier@elka.pw.edu.pl> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from parcelfarce.linux.theplanet.co.uk ([195.92.249.252]:59861 "EHLO www.linux.org.uk") by vger.kernel.org with ESMTP id S264622AbUESWcH (ORCPT ); Wed, 19 May 2004 18:32:07 -0400 In-Reply-To: <200405191851.06281.bzolnier@elka.pw.edu.pl> List-Id: linux-ide@vger.kernel.org To: Bartlomiej Zolnierkiewicz Cc: Go Taniguchi , linux-ide@vger.kernel.org, "Nakajima, Jun" (added Jun to CC) Bartlomiej Zolnierkiewicz wrote: > On Tuesday 18 of May 2004 13:19, Go Taniguchi wrote: >>If speed is XFER_UDMA_6, base clock is set to low base clock. >>It should be "speed >= XFER_UDMA_5". My ICH6 system reported XFER_UDMA_6, > > > Jeff, does ICH6 support UDMA6? > ICH5 doesn't but ata_piix.c allows it. Good question. AFAICS ICH5 and ICH6 are the same such that: * PATA does not support UDMA6 * internal base clock is 133Mhz for UDMA5 * SATA PCI device exports, but completely ignores, PATA timing registers So for ata_piix at least, I would prefer to do * patch1: your patch, based on Go's patch * patch2: only configure timing registers for PATA port (PATA is only used when an #ifdef is defined) * patch3: do not limit SATA to udma5 Jeff