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X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nRTVPiBDCQm4rqIyg0up3YH8613smCcjPPJJFSUs4mnIlRtJUPYlN3CdJL1j9TWcb4QuS7R5Y2j8ZuCViOs6Dg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB7585 X-OriginatorOrg: intel.com X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Intel-xe" X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Karthik, On 16-10-2026 00:37, Karthik Poosa wrote: > Provide a pcode write helper that keeps the mailbox lock held while issuing > an ordered sequence of writes. > This will be used while writing the fan table ensuring that is not > interleaved by any other pcode mailbox command. > > Signed-off-by: Karthik Poosa > --- > drivers/gpu/drm/xe/xe_pcode.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/xe/xe_pcode.h | 7 +++++++ > 2 files changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c > index 266deecbb100..ca107b0234d9 100644 > --- a/drivers/gpu/drm/xe/xe_pcode.c > +++ b/drivers/gpu/drm/xe/xe_pcode.c > @@ -124,6 +124,26 @@ int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 data, int timeout > return err; > } > > +int xe_pcode_write_batch(struct xe_tile *tile, const struct xe_pcode_write *writes, > + unsigned int count) > +{ > + unsigned int i; > + int err = 0; > + > + mutex_lock(&tile->pcode.lock); nit: if count == 0 then return immediately without acquiring the mutex. > + for (i = 0; i < count; i++) { > + u32 data = writes[i].data; > + > + err = pcode_mailbox_rw(tile, writes[i].mbox, &data, NULL, PCODE_DEFAULT_TIMEOUT_MS, > + false, false); > + if (err) Use a debug print in case of failure for clarity. Regards, Soham > + break; > + } > + mutex_unlock(&tile->pcode.lock); > + > + return err; > +} > + > int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, u32 data1, int timeout) > { > int err; > diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h > index 7e43792b0037..74bd553ab390 100644 > --- a/drivers/gpu/drm/xe/xe_pcode.h > +++ b/drivers/gpu/drm/xe/xe_pcode.h > @@ -18,6 +18,11 @@ struct xe_pcode_version { > u32 engg; > }; > > +struct xe_pcode_write { > + u32 mbox; > + u32 data; > +}; > + > #define PCODE_DEFAULT_TIMEOUT_MS 10 > > int xe_pcode_init_early(struct xe_tile *tile); > @@ -28,6 +33,8 @@ int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq, > int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val0, u32 *val1); > int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val, > int timeout_ms); > +int xe_pcode_write_batch(struct xe_tile *tile, const struct xe_pcode_write *writes, > + unsigned int count); > int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, > u32 data1, int timeout); > int xe_get_pcode_version(struct xe_device *xe, struct xe_pcode_version *version);