From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Philippe Bergheaud <felix@linux.ibm.com>, linuxppc-dev@lists.ozlabs.org
Cc: fbarrat@linux.ibm.com, clombard@linux.ibm.com,
Philippe Bergheaud <felix@linux.ibm.com>,
benh@au1.ibm.com
Subject: Re: [v4, 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode
Date: Fri, 18 May 2018 00:54:59 +1000 (AEST) [thread overview]
Message-ID: <40mvVC0w17z9s4V@ozlabs.org> (raw)
In-Reply-To: <20180514082736.3699-1-felix@linux.ibm.com>
On Mon, 2018-05-14 at 08:27:35 UTC, Philippe Bergheaud wrote:
> Skiboot used to set the default Tunnel BAR register value when capi mode
> was enabled. This approach was ok for the cxl driver, but prevented other
> drivers from choosing different values.
>
> Skiboot versions > 5.11 will not set the default value any longer. This
> patch modifies the cxl driver to set/reset the Tunnel BAR register when
> entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar().
>
> That should work with old skiboot (since we are re-writing the value
> already set) and new skiboot.
>
> Signed-off-by: Philippe Bergheaud <felix@linux.ibm.com>
> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Series applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/401dca8cbd14fc4b32d93499dcd12a
cheers
prev parent reply other threads:[~2018-05-17 14:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-14 8:27 [PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode Philippe Bergheaud
2018-05-14 8:27 ` [PATCH v4 2/2] cxl: Report the tunneled operations status Philippe Bergheaud
2018-05-16 16:47 ` Frederic Barrat
2018-05-14 10:51 ` [PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode Michael Ellerman
2018-05-14 13:00 ` Philippe Bergheaud
2018-05-15 5:30 ` Michael Ellerman
2018-05-15 8:54 ` Philippe Bergheaud
2018-05-17 14:54 ` Michael Ellerman [this message]
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