From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A144EC433F5 for ; Tue, 7 Dec 2021 14:27:27 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3EE5280F81; Tue, 7 Dec 2021 15:27:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=foss.st.com header.i=@foss.st.com header.b="H402HFSY"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 95C17810ED; Tue, 7 Dec 2021 15:27:23 +0100 (CET) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0ABE68069E for ; Tue, 7 Dec 2021 15:27:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=prvs=6975ae474c=patrick.delaunay@foss.st.com Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1B793quZ003477; Tue, 7 Dec 2021 15:27:09 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=yCLCHNrV/tI1apk/zCwK196RLmdjkVReYADf8g9FBeQ=; b=H402HFSYisKWnHRe1wO/mIC6JPT87/dRTKM9K6j1IXm7nRdxseMC6+7ph3xK1Pci6cfH u0fVg9zgMMBHUrlLR5k8zQXM3RSW0/h6s6gaKzFRTeDB+VpKu8xjgZcq9MEH+8a1R3ug KXLOnxfSw7nfJc1sv+tn9yxaL4cldL21cZprB/2eMLAp7/HfhgS01N3cMRTfZe7K/8B1 G02fqdOcNtBSk08A5glO7KaR6eYfT6aCSpWf7XCUkt+YesgW1pahfkrOQPfBRLvOtETi zbatHvrNHay0L5/pRMYJAfsLgRNuyD+ZFRmq1/bTu8puJrwCRJWukAH2rb8aA1VQF5Lp wA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3csmx0np88-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Dec 2021 15:27:09 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 055FA100034; Tue, 7 Dec 2021 15:27:07 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EE01E220887; Tue, 7 Dec 2021 15:27:06 +0100 (CET) Received: from lmecxl0994.lme.st.com (10.75.127.48) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Tue, 7 Dec 2021 15:27:05 +0100 Subject: Re: [RFC PATCH 06/10] FWU: STM32MP1: Add support to read boot index from backup register To: Sughosh Ganu , CC: Patrice Chotard , Heinrich Schuchardt , Alexander Graf , Simon Glass , Bin Meng , Peng Fan , AKASHI Takahiro , Ilias Apalodimas , Jose Marinho , Grant Likely , Jason Liu References: <20211125070146.2389-1-sughosh.ganu@linaro.org> <20211125070146.2389-7-sughosh.ganu@linaro.org> From: Patrick DELAUNAY Message-ID: <4102ae4d-e441-514b-cab7-4832cc7cfa9a@foss.st.com> Date: Tue, 7 Dec 2021 15:27:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211125070146.2389-7-sughosh.ganu@linaro.org> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-07_06,2021-12-06_02,2021-12-02_01 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Sughosh, On 11/25/21 8:01 AM, Sughosh Ganu wrote: > The FWU Multi Bank Update feature allows the platform to boot the > firmware images from one of the partitions(banks). The first stage > bootloader(fsbl) passes the value of the boot index, i.e. the bank > from which the firmware images were booted from to U-Boot. On the > STM32MP157C-DK2 board, this value is passed through one of the SoC's > backup register. Add a function to read the boot index value from the > backup register. > > Signed-off-by: Sughosh Ganu > --- > arch/arm/mach-stm32mp/include/mach/stm32.h | 1 + > board/st/stm32mp1/stm32mp1.c | 7 +++++++ > include/fwu_metadata.h | 1 + > 3 files changed, 9 insertions(+) > > diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h > index c11a9903f2..21ed9f12e4 100644 > --- a/arch/arm/mach-stm32mp/include/mach/stm32.h > +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h > @@ -97,6 +97,7 @@ enum boot_device { > #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) > #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) > #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) > +#define TAMP_FWU_BOOT_IDX TAMP_BACKUP_REGISTER(10) The used TAMP register need to be aligned with TF-A BL2, offset = 10 to be confirmed > #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) > #define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) > #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) > diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c > index a6884d2772..32bba71289 100644 > --- a/board/st/stm32mp1/stm32mp1.c > +++ b/board/st/stm32mp1/stm32mp1.c > @@ -990,6 +990,13 @@ int fwu_plat_get_blk_desc(struct blk_desc **desc) > return 0; > } > > +void fwu_plat_get_bootidx(void *boot_idx) > +{ > + u32 *bootidx = boot_idx; > + > + *bootidx = readl(TAMP_FWU_BOOT_IDX); > +} > + > struct fwu_metadata_ops *get_plat_fwu_metadata_ops(void) > { > if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) && > diff --git a/include/fwu_metadata.h b/include/fwu_metadata.h > index 6a5e814ab6..44f06f4c6a 100644 > --- a/include/fwu_metadata.h > +++ b/include/fwu_metadata.h > @@ -124,5 +124,6 @@ int fwu_get_metadata(struct fwu_metadata **metadata); > > int fwu_plat_get_update_index(u32 *update_idx); > int fwu_plat_get_blk_desc(struct blk_desc **desc); > +void fwu_plat_get_bootidx(void *boot_idx); > > #endif /* _FWU_METADATA_H_ */ Regards Patrick