diff for duplicates of <4123121.bNYOPIrL2s@diego> diff --git a/a/1.txt b/N1/1.txt index 1c7d6ec..5401511 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,19 +1,18 @@ Hi Stephen, Am Dienstag, 22. September 2015, 16:19:00 schrieb Stephen Boyd: -> On 09/23, Heiko St=FCbner wrote: +> On 09/23, Heiko Stübner wrote: > > Am Dienstag, 22. September 2015, 15:41:25 schrieb Stephen Boyd: > > > On 09/17, Xing Zheng wrote: > > > > + > > > > +static void rockchip_rk3036_pll_init(struct clk_hw *hw) -> > >=20 +> > > > > > init ops are "discouraged". Could we do this through assigned > > > rates instead? -> >=20 -> > really? According to Mike that was a valid use-case when we looked = -for an +> > +> > really? According to Mike that was a valid use-case when we looked for an > > initial place for that on the rk3288 :-) . ->=20 +> > A comment in clk.c indicates init ops are discouraged. Maybe this > is a valid use-case on other platforms so it was allowed, but > pretty much every time we see a new init op we have to think @@ -25,54 +24,45 @@ callback!" [0] so it looks like he was convinced of our reasoning at the time :-) . -[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/0= -01570.html +[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/001570.html > > > > +{ -> > > > +=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); -> > > > +=09const struct rockchip_pll_rate_table *rate; -> > > > +=09unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac= -; -> > > > +=09unsigned long drate; -> > > > +=09u32 pllcon; +> > > > + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +> > > > + const struct rockchip_pll_rate_table *rate; +> > > > + unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac; +> > > > + unsigned long drate; +> > > > + u32 pllcon; > > > > + -> > > > +=09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) -> > > > +=09=09return; -> > >=20 -> > > I don't understand what this one does though. This check isn't in= - +> > > > + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) +> > > > + return; +> > > +> > > I don't understand what this one does though. This check isn't in > > > the set rate ops. -> >=20 +> > > > And it shouldn't be :-) -> >=20 -> > The issue this whole thing is trying to solve is aligning the pll s= -ettings +> > +> > The issue this whole thing is trying to solve is aligning the pll settings > > which what we have in the rate table, not what the bootloader set. -> >=20 -> > For example the bootloader could set up a pll at 594MHz with one se= -t of +> > +> > For example the bootloader could set up a pll at 594MHz with one set of > > parameters and after some time - when you don't want to exchange > > bootloaders on shipping devices anymore - it comes to light that a -> > different set of parameters for the same frequency produces for exa= -mple a -> > more stable hdmi signal [I think that was the main reason for the i= -nitial +> > different set of parameters for the same frequency produces for example a +> > more stable hdmi signal [I think that was the main reason for the initial > > change]. -> >=20 -> > So we're not changing the frequency x -> y, which could be easily d= -one +> > +> > So we're not changing the frequency x -> y, which could be easily done > > [and is done already] via assigned-rates, but instead -> >=20 -> > =09x {params a,b,c} -> x {params d,e,f} -> >=20 -> > so the rate itself stays the same, only the frequency generation is= - +> > +> > x {params a,b,c} -> x {params d,e,f} +> > +> > so the rate itself stays the same, only the frequency generation is > > adapted. > Ok. It would be nice if this sort of information was made into a > comment and put in the code. Or at least the commit text for the > change. ->=20 +> > And is there any reason that we need to get the parent clock and > parent rate to align the PLL settings? > It would be nice if we @@ -86,8 +76,7 @@ below actually does work quite nicely on rk3288 boards. ---------------- 8< -------------------- From: Heiko Stuebner <heiko@sntech.de> -Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-cal= -lback +Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-callback Separate the update of pll registers from the actual set_rate function so that the init callback does not need to access clk-API functions. @@ -97,247 +86,216 @@ we can also directly use these new functions in other places too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- - drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++-----------= --------- + drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++------------------- 1 file changed, 74 insertions(+), 61 deletions(-) -diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-= -pll.c +diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 7737a1d..4881eb8 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c -@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip= -_clk_pll *pll) - #define RK3066_PLLCON3_PWRDOWN=09=09(1 << 1) - #define RK3066_PLLCON3_BYPASS=09=09(1 << 0) -=20 -+static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pl= -l, -+=09=09=09=09=09struct rockchip_pll_rate_table *rate) +@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) + #define RK3066_PLLCON3_PWRDOWN (1 << 1) + #define RK3066_PLLCON3_BYPASS (1 << 0) + ++static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, ++ struct rockchip_pll_rate_table *rate) +{ -+=09u32 pllcon; ++ u32 pllcon; + -+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); -+=09rate->nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT) -+=09=09=09=09& RK3066_PLLCON0_NR_MASK) + 1; -+=09rate->no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT) -+=09=09=09=09& RK3066_PLLCON0_OD_MASK) + 1; ++ pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); ++ rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) ++ & RK3066_PLLCON0_NR_MASK) + 1; ++ rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) ++ & RK3066_PLLCON0_OD_MASK) + 1; + -+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); -+=09rate->nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT) -+=09=09=09=09& RK3066_PLLCON1_NF_MASK) + 1; ++ pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); ++ rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) ++ & RK3066_PLLCON1_NF_MASK) + 1; + -+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); -+=09rate->nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT) -+=09=09=09=09& RK3066_PLLCON2_NB_MASK) + 1; ++ pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); ++ rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) ++ & RK3066_PLLCON2_NB_MASK) + 1; +} + - static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw= -, - =09=09=09=09=09=09 unsigned long prate) + static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) { - =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); --=09u64 nf, nr, no, rate64 =3D prate; -+=09struct rockchip_pll_rate_table cur; -+=09u64 rate64 =3D prate; - =09u32 pllcon; -=20 - =09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); -@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_r= -ate(struct clk_hw *hw, - =09=09return prate; - =09} -=20 --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); --=09nf =3D (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK= -; + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +- u64 nf, nr, no, rate64 = prate; ++ struct rockchip_pll_rate_table cur; ++ u64 rate64 = prate; + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); +@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, + return prate; + } + +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); +- nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK; - --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); --=09nr =3D (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK= -; --=09no =3D (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK= -; -+=09rockchip_rk3066_pll_get_params(pll, &cur); -=20 --=09rate64 *=3D (nf + 1); --=09do_div(rate64, nr + 1); --=09do_div(rate64, no + 1); -+=09rate64 *=3D cur.nf; -+=09do_div(rate64, cur.nr); -+=09do_div(rate64, cur.no); -=20 - =09return (unsigned long)rate64; +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); +- nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK; +- no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK; ++ rockchip_rk3066_pll_get_params(pll, &cur); + +- rate64 *= (nf + 1); +- do_div(rate64, nr + 1); +- do_div(rate64, no + 1); ++ rate64 *= cur.nf; ++ do_div(rate64, cur.nr); ++ do_div(rate64, cur.no); + + return (unsigned long)rate64; } -=20 --static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo= -ng drate, --=09=09=09=09=09unsigned long prate) -+static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll= -, -+=09=09=09=09const struct rockchip_pll_rate_table *rate) + +-static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, +- unsigned long prate) ++static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, ++ const struct rockchip_pll_rate_table *rate) { --=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); --=09const struct rockchip_pll_rate_table *rate; --=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat= -e); --=09struct regmap *grf =3D rockchip_clk_get_grf(); --=09struct clk_mux *pll_mux =3D &pll->pll_mux; - =09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops; -+=09struct clk_mux *pll_mux =3D &pll->pll_mux; -+=09struct rockchip_pll_rate_table cur; - =09int rate_change_remuxed =3D 0; - =09int cur_parent; - =09int ret; -=20 --=09if (IS_ERR(grf)) { --=09=09pr_debug("%s: grf regmap not available, aborting rate change\n",= - --=09=09=09 __func__); --=09=09return PTR_ERR(grf); --=09} +- struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +- const struct rockchip_pll_rate_table *rate; +- unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); +- struct regmap *grf = rockchip_clk_get_grf(); +- struct clk_mux *pll_mux = &pll->pll_mux; + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; ++ struct clk_mux *pll_mux = &pll->pll_mux; ++ struct rockchip_pll_rate_table cur; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + +- if (IS_ERR(grf)) { +- pr_debug("%s: grf regmap not available, aborting rate change\n", +- __func__); +- return PTR_ERR(grf); +- } - --=09pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu= -\n", --=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate); +- pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", +- __func__, clk_hw_get_name(hw), old_rate, drate, prate); - --=09/* Get required rate settings from table */ --=09rate =3D rockchip_get_pll_settings(pll, drate); --=09if (!rate) { --=09=09pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, --=09=09=09drate, clk_hw_get_name(hw)); --=09=09return -EINVAL; --=09} +- /* Get required rate settings from table */ +- rate = rockchip_get_pll_settings(pll, drate); +- if (!rate) { +- pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, +- drate, clk_hw_get_name(hw)); +- return -EINVAL; +- } - - =09pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", - =09=09 __func__, rate->rate, rate->nr, rate->no, rate->nf); -=20 -+=09rockchip_rk3066_pll_get_params(pll, &cur); -+=09cur.rate =3D 0; + pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", + __func__, rate->rate, rate->nr, rate->no, rate->nf); + ++ rockchip_rk3066_pll_get_params(pll, &cur); ++ cur.rate = 0; + - =09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); - =09if (cur_parent =3D=3D PLL_MODE_NORM) { - =09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); -@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_= -hw *hw, unsigned long drate, - =09/* wait for the pll to lock */ - =09ret =3D rockchip_pll_wait_lock(pll); - =09if (ret) { --=09=09pr_warn("%s: pll did not lock, trying to restore old rate %lu\n"= -, --=09=09=09__func__, old_rate); --=09=09rockchip_rk3066_pll_set_rate(hw, old_rate, prate); -+=09=09pr_warn("%s: pll update unsucessful, trying to restore old param= -s\n", -+=09=09=09__func__); -+=09=09rockchip_rk3066_pll_set_params(pll, &cur); - =09} -=20 - =09if (rate_change_remuxed) -@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk= -_hw *hw, unsigned long drate, - =09return ret; + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); +@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, + /* wait for the pll to lock */ + ret = rockchip_pll_wait_lock(pll); + if (ret) { +- pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", +- __func__, old_rate); +- rockchip_rk3066_pll_set_rate(hw, old_rate, prate); ++ pr_warn("%s: pll update unsucessful, trying to restore old params\n", ++ __func__); ++ rockchip_rk3066_pll_set_params(pll, &cur); + } + + if (rate_change_remuxed) +@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, + return ret; } -=20 -+static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo= -ng drate, -+=09=09=09=09=09unsigned long prate) + ++static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, ++ unsigned long prate) +{ -+=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); -+=09const struct rockchip_pll_rate_table *rate; -+=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat= -e); -+=09struct regmap *grf =3D rockchip_clk_get_grf(); ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ const struct rockchip_pll_rate_table *rate; ++ unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); ++ struct regmap *grf = rockchip_clk_get_grf(); + -+=09if (IS_ERR(grf)) { -+=09=09pr_debug("%s: grf regmap not available, aborting rate change\n",= - -+=09=09=09 __func__); -+=09=09return PTR_ERR(grf); -+=09} ++ if (IS_ERR(grf)) { ++ pr_debug("%s: grf regmap not available, aborting rate change\n", ++ __func__); ++ return PTR_ERR(grf); ++ } + -+=09pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu= -\n", -+=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate); ++ pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", ++ __func__, clk_hw_get_name(hw), old_rate, drate, prate); + -+=09/* Get required rate settings from table */ -+=09rate =3D rockchip_get_pll_settings(pll, drate); -+=09if (!rate) { -+=09=09pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, -+=09=09=09drate, clk_hw_get_name(hw)); -+=09=09return -EINVAL; -+=09} ++ /* Get required rate settings from table */ ++ rate = rockchip_get_pll_settings(pll, drate); ++ if (!rate) { ++ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, ++ drate, clk_hw_get_name(hw)); ++ return -EINVAL; ++ } + -+=09return rockchip_rk3066_pll_set_params(pll, rate); ++ return rockchip_rk3066_pll_set_params(pll, rate); +} + static int rockchip_rk3066_pll_enable(struct clk_hw *hw) { - =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); -@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw = -*hw) + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) { - =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); - =09const struct rockchip_pll_rate_table *rate; --=09unsigned int nf, nr, no, nb; -+=09struct rockchip_pll_rate_table cur; - =09unsigned long drate; --=09u32 pllcon; -=20 - =09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) - =09=09return; -@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_h= -w *hw) - =09if (!rate) - =09=09return; -=20 --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); --=09nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MAS= -K) + 1; --=09no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MAS= -K) + 1; + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; +- unsigned int nf, nr, no, nb; ++ struct rockchip_pll_rate_table cur; + unsigned long drate; +- u32 pllcon; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return; +@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) + if (!rate) + return; + +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); +- nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1; +- no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1; - --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); --=09nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MAS= -K) + 1; +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); +- nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1; - --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); --=09nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MAS= -K) + 1; -+=09rockchip_rk3066_pll_get_params(pll, &cur); -=20 - =09pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:= -%d)\n", --=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, nr, --=09=09rate->no, no, rate->nf, nf, rate->nb, nb); --=09if (rate->nr !=3D nr || rate->no !=3D no || rate->nf !=3D nf --=09=09=09=09=09 || rate->nb !=3D nb) { --=09=09struct clk_hw *parent =3D clk_hw_get_parent(hw); --=09=09unsigned long prate; +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); +- nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MASK) + 1; ++ rockchip_rk3066_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", +- __func__, clk_hw_get_name(hw), drate, rate->nr, nr, +- rate->no, no, rate->nf, nf, rate->nb, nb); +- if (rate->nr != nr || rate->no != no || rate->nf != nf +- || rate->nb != nb) { +- struct clk_hw *parent = clk_hw_get_parent(hw); +- unsigned long prate; - --=09=09if (!parent) { --=09=09=09pr_warn("%s: parent of %s not available\n", --=09=09=09=09__func__, clk_hw_get_name(hw)); -+=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, -+=09=09 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); -+=09if (rate->nr !=3D cur.nr || rate->no !=3D cur.no || rate->nf !=3D c= -ur.nf -+=09=09=09=09=09=09 || rate->nb !=3D cur.nb) { -+=09=09struct regmap *grf =3D rockchip_clk_get_grf(); +- if (!parent) { +- pr_warn("%s: parent of %s not available\n", +- __func__, clk_hw_get_name(hw)); ++ __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, ++ rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); ++ if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf ++ || rate->nb != cur.nb) { ++ struct regmap *grf = rockchip_clk_get_grf(); + -+=09=09if (IS_ERR(grf)) - =09=09=09return; --=09=09} -=20 - =09=09pr_debug("%s: pll %s: rate params do not match rate table, adjus= -ting\n", - =09=09=09 __func__, clk_hw_get_name(hw)); --=09=09prate =3D clk_hw_get_rate(parent); --=09=09rockchip_rk3066_pll_set_rate(hw, drate, prate); -+=09=09rockchip_rk3066_pll_set_params(pll, rate); - =09} ++ if (IS_ERR(grf)) + return; +- } + + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); +- prate = clk_hw_get_rate(parent); +- rockchip_rk3066_pll_set_rate(hw, drate, prate); ++ rockchip_rk3066_pll_set_params(pll, rate); + } } -=20 ---=20 + +-- 2.5.3 ---------------- 8< -------------------- diff --git a/a/content_digest b/N1/content_digest index 1b2b05a..1bacafa 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -16,19 +16,18 @@ "Hi Stephen,\n" "\n" "Am Dienstag, 22. September 2015, 16:19:00 schrieb Stephen Boyd:\n" - "> On 09/23, Heiko St=FCbner wrote:\n" + "> On 09/23, Heiko St\303\274bner wrote:\n" "> > Am Dienstag, 22. September 2015, 15:41:25 schrieb Stephen Boyd:\n" "> > > On 09/17, Xing Zheng wrote:\n" "> > > > +\n" "> > > > +static void rockchip_rk3036_pll_init(struct clk_hw *hw)\n" - "> > >=20\n" + "> > > \n" "> > > init ops are \"discouraged\". Could we do this through assigned\n" "> > > rates instead?\n" - "> >=20\n" - "> > really? According to Mike that was a valid use-case when we looked =\n" - "for an\n" + "> > \n" + "> > really? According to Mike that was a valid use-case when we looked for an\n" "> > initial place for that on the rk3288 :-) .\n" - ">=20\n" + "> \n" "> A comment in clk.c indicates init ops are discouraged. Maybe this\n" "> is a valid use-case on other platforms so it was allowed, but\n" "> pretty much every time we see a new init op we have to think\n" @@ -40,54 +39,45 @@ "so it looks like he was convinced of our reasoning at the time :-) .\n" "\n" "\n" - "[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/0=\n" - "01570.html\n" + "[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/001570.html\n" "\n" "\n" "> > > > +{\n" - "> > > > +=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "> > > > +=09const struct rockchip_pll_rate_table *rate;\n" - "> > > > +=09unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac=\n" - ";\n" - "> > > > +=09unsigned long drate;\n" - "> > > > +=09u32 pllcon;\n" + "> > > > +\tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "> > > > +\tconst struct rockchip_pll_rate_table *rate;\n" + "> > > > +\tunsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac;\n" + "> > > > +\tunsigned long drate;\n" + "> > > > +\tu32 pllcon;\n" "> > > > +\n" - "> > > > +=09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" - "> > > > +=09=09return;\n" - "> > >=20\n" - "> > > I don't understand what this one does though. This check isn't in=\n" - "\n" + "> > > > +\tif (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" + "> > > > +\t\treturn;\n" + "> > > \n" + "> > > I don't understand what this one does though. This check isn't in\n" "> > > the set rate ops.\n" - "> >=20\n" + "> > \n" "> > And it shouldn't be :-)\n" - "> >=20\n" - "> > The issue this whole thing is trying to solve is aligning the pll s=\n" - "ettings\n" + "> > \n" + "> > The issue this whole thing is trying to solve is aligning the pll settings\n" "> > which what we have in the rate table, not what the bootloader set.\n" - "> >=20\n" - "> > For example the bootloader could set up a pll at 594MHz with one se=\n" - "t of\n" + "> > \n" + "> > For example the bootloader could set up a pll at 594MHz with one set of\n" "> > parameters and after some time - when you don't want to exchange\n" "> > bootloaders on shipping devices anymore - it comes to light that a\n" - "> > different set of parameters for the same frequency produces for exa=\n" - "mple a\n" - "> > more stable hdmi signal [I think that was the main reason for the i=\n" - "nitial\n" + "> > different set of parameters for the same frequency produces for example a\n" + "> > more stable hdmi signal [I think that was the main reason for the initial\n" "> > change].\n" - "> >=20\n" - "> > So we're not changing the frequency x -> y, which could be easily d=\n" - "one\n" + "> > \n" + "> > So we're not changing the frequency x -> y, which could be easily done\n" "> > [and is done already] via assigned-rates, but instead\n" - "> >=20\n" - "> > =09x {params a,b,c} -> x {params d,e,f}\n" - "> >=20\n" - "> > so the rate itself stays the same, only the frequency generation is=\n" - "\n" + "> > \n" + "> > \tx {params a,b,c} -> x {params d,e,f}\n" + "> > \n" + "> > so the rate itself stays the same, only the frequency generation is\n" "> > adapted.\n" "> Ok. It would be nice if this sort of information was made into a\n" "> comment and put in the code. Or at least the commit text for the\n" "> change.\n" - ">=20\n" + "> \n" "> And is there any reason that we need to get the parent clock and\n" "> parent rate to align the PLL settings?\n" "> It would be nice if we\n" @@ -101,8 +91,7 @@ "\n" "---------------- 8< --------------------\n" "From: Heiko Stuebner <heiko@sntech.de>\n" - "Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-cal=\n" - "lback\n" + "Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-callback\n" "\n" "Separate the update of pll registers from the actual set_rate function\n" "so that the init callback does not need to access clk-API functions.\n" @@ -112,250 +101,219 @@ "\n" "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" "---\n" - " drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++-----------=\n" - "--------\n" + " drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++-------------------\n" " 1 file changed, 74 insertions(+), 61 deletions(-)\n" "\n" - "diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-=\n" - "pll.c\n" + "diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c\n" "index 7737a1d..4881eb8 100644\n" "--- a/drivers/clk/rockchip/clk-pll.c\n" "+++ b/drivers/clk/rockchip/clk-pll.c\n" - "@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip=\n" - "_clk_pll *pll)\n" - " #define RK3066_PLLCON3_PWRDOWN=09=09(1 << 1)\n" - " #define RK3066_PLLCON3_BYPASS=09=09(1 << 0)\n" - "=20\n" - "+static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pl=\n" - "l,\n" - "+=09=09=09=09=09struct rockchip_pll_rate_table *rate)\n" + "@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)\n" + " #define RK3066_PLLCON3_PWRDOWN\t\t(1 << 1)\n" + " #define RK3066_PLLCON3_BYPASS\t\t(1 << 0)\n" + " \n" + "+static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,\n" + "+\t\t\t\t\tstruct rockchip_pll_rate_table *rate)\n" "+{\n" - "+=09u32 pllcon;\n" + "+\tu32 pllcon;\n" "+\n" - "+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" - "+=09rate->nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON0_NR_MASK) + 1;\n" - "+=09rate->no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON0_OD_MASK) + 1;\n" + "+\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" + "+\trate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON0_NR_MASK) + 1;\n" + "+\trate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON0_OD_MASK) + 1;\n" "+\n" - "+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" - "+=09rate->nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON1_NF_MASK) + 1;\n" + "+\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" + "+\trate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON1_NF_MASK) + 1;\n" "+\n" - "+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" - "+=09rate->nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON2_NB_MASK) + 1;\n" + "+\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" + "+\trate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON2_NB_MASK) + 1;\n" "+}\n" "+\n" - " static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw=\n" - ",\n" - " =09=09=09=09=09=09 unsigned long prate)\n" + " static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,\n" + " \t\t\t\t\t\t unsigned long prate)\n" " {\n" - " =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "-=09u64 nf, nr, no, rate64 =3D prate;\n" - "+=09struct rockchip_pll_rate_table cur;\n" - "+=09u64 rate64 =3D prate;\n" - " =09u32 pllcon;\n" - "=20\n" - " =09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(3));\n" - "@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_r=\n" - "ate(struct clk_hw *hw,\n" - " =09=09return prate;\n" - " =09}\n" - "=20\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" - "-=09nf =3D (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK=\n" - ";\n" + " \tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "-\tu64 nf, nr, no, rate64 = prate;\n" + "+\tstruct rockchip_pll_rate_table cur;\n" + "+\tu64 rate64 = prate;\n" + " \tu32 pllcon;\n" + " \n" + " \tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));\n" + "@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,\n" + " \t\treturn prate;\n" + " \t}\n" + " \n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" + "-\tnf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK;\n" "-\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" - "-=09nr =3D (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK=\n" - ";\n" - "-=09no =3D (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK=\n" - ";\n" - "+=09rockchip_rk3066_pll_get_params(pll, &cur);\n" - "=20\n" - "-=09rate64 *=3D (nf + 1);\n" - "-=09do_div(rate64, nr + 1);\n" - "-=09do_div(rate64, no + 1);\n" - "+=09rate64 *=3D cur.nf;\n" - "+=09do_div(rate64, cur.nr);\n" - "+=09do_div(rate64, cur.no);\n" - "=20\n" - " =09return (unsigned long)rate64;\n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" + "-\tnr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK;\n" + "-\tno = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK;\n" + "+\trockchip_rk3066_pll_get_params(pll, &cur);\n" + " \n" + "-\trate64 *= (nf + 1);\n" + "-\tdo_div(rate64, nr + 1);\n" + "-\tdo_div(rate64, no + 1);\n" + "+\trate64 *= cur.nf;\n" + "+\tdo_div(rate64, cur.nr);\n" + "+\tdo_div(rate64, cur.no);\n" + " \n" + " \treturn (unsigned long)rate64;\n" " }\n" - "=20\n" - "-static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo=\n" - "ng drate,\n" - "-=09=09=09=09=09unsigned long prate)\n" - "+static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll=\n" - ",\n" - "+=09=09=09=09const struct rockchip_pll_rate_table *rate)\n" + " \n" + "-static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + "-\t\t\t\t\tunsigned long prate)\n" + "+static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,\n" + "+\t\t\t\tconst struct rockchip_pll_rate_table *rate)\n" " {\n" - "-=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "-=09const struct rockchip_pll_rate_table *rate;\n" - "-=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat=\n" - "e);\n" - "-=09struct regmap *grf =3D rockchip_clk_get_grf();\n" - "-=09struct clk_mux *pll_mux =3D &pll->pll_mux;\n" - " =09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops;\n" - "+=09struct clk_mux *pll_mux =3D &pll->pll_mux;\n" - "+=09struct rockchip_pll_rate_table cur;\n" - " =09int rate_change_remuxed =3D 0;\n" - " =09int cur_parent;\n" - " =09int ret;\n" - "=20\n" - "-=09if (IS_ERR(grf)) {\n" - "-=09=09pr_debug(\"%s: grf regmap not available, aborting rate change\\n\",=\n" - "\n" - "-=09=09=09 __func__);\n" - "-=09=09return PTR_ERR(grf);\n" - "-=09}\n" + "-\tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "-\tconst struct rockchip_pll_rate_table *rate;\n" + "-\tunsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);\n" + "-\tstruct regmap *grf = rockchip_clk_get_grf();\n" + "-\tstruct clk_mux *pll_mux = &pll->pll_mux;\n" + " \tconst struct clk_ops *pll_mux_ops = pll->pll_mux_ops;\n" + "+\tstruct clk_mux *pll_mux = &pll->pll_mux;\n" + "+\tstruct rockchip_pll_rate_table cur;\n" + " \tint rate_change_remuxed = 0;\n" + " \tint cur_parent;\n" + " \tint ret;\n" + " \n" + "-\tif (IS_ERR(grf)) {\n" + "-\t\tpr_debug(\"%s: grf regmap not available, aborting rate change\\n\",\n" + "-\t\t\t __func__);\n" + "-\t\treturn PTR_ERR(grf);\n" + "-\t}\n" "-\n" - "-=09pr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu=\n" - "\\n\",\n" - "-=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" + "-\tpr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu\\n\",\n" + "-\t\t __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" "-\n" - "-=09/* Get required rate settings from table */\n" - "-=09rate =3D rockchip_get_pll_settings(pll, drate);\n" - "-=09if (!rate) {\n" - "-=09=09pr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" - "-=09=09=09drate, clk_hw_get_name(hw));\n" - "-=09=09return -EINVAL;\n" - "-=09}\n" + "-\t/* Get required rate settings from table */\n" + "-\trate = rockchip_get_pll_settings(pll, drate);\n" + "-\tif (!rate) {\n" + "-\t\tpr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" + "-\t\t\tdrate, clk_hw_get_name(hw));\n" + "-\t\treturn -EINVAL;\n" + "-\t}\n" "-\n" - " =09pr_debug(\"%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\\n\",\n" - " =09=09 __func__, rate->rate, rate->nr, rate->no, rate->nf);\n" - "=20\n" - "+=09rockchip_rk3066_pll_get_params(pll, &cur);\n" - "+=09cur.rate =3D 0;\n" + " \tpr_debug(\"%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\\n\",\n" + " \t\t __func__, rate->rate, rate->nr, rate->no, rate->nf);\n" + " \n" + "+\trockchip_rk3066_pll_get_params(pll, &cur);\n" + "+\tcur.rate = 0;\n" "+\n" - " =09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw);\n" - " =09if (cur_parent =3D=3D PLL_MODE_NORM) {\n" - " =09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" - "@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_=\n" - "hw *hw, unsigned long drate,\n" - " =09/* wait for the pll to lock */\n" - " =09ret =3D rockchip_pll_wait_lock(pll);\n" - " =09if (ret) {\n" - "-=09=09pr_warn(\"%s: pll did not lock, trying to restore old rate %lu\\n\"=\n" - ",\n" - "-=09=09=09__func__, old_rate);\n" - "-=09=09rockchip_rk3066_pll_set_rate(hw, old_rate, prate);\n" - "+=09=09pr_warn(\"%s: pll update unsucessful, trying to restore old param=\n" - "s\\n\",\n" - "+=09=09=09__func__);\n" - "+=09=09rockchip_rk3066_pll_set_params(pll, &cur);\n" - " =09}\n" - "=20\n" - " =09if (rate_change_remuxed)\n" - "@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk=\n" - "_hw *hw, unsigned long drate,\n" - " =09return ret;\n" + " \tcur_parent = pll_mux_ops->get_parent(&pll_mux->hw);\n" + " \tif (cur_parent == PLL_MODE_NORM) {\n" + " \t\tpll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" + "@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + " \t/* wait for the pll to lock */\n" + " \tret = rockchip_pll_wait_lock(pll);\n" + " \tif (ret) {\n" + "-\t\tpr_warn(\"%s: pll did not lock, trying to restore old rate %lu\\n\",\n" + "-\t\t\t__func__, old_rate);\n" + "-\t\trockchip_rk3066_pll_set_rate(hw, old_rate, prate);\n" + "+\t\tpr_warn(\"%s: pll update unsucessful, trying to restore old params\\n\",\n" + "+\t\t\t__func__);\n" + "+\t\trockchip_rk3066_pll_set_params(pll, &cur);\n" + " \t}\n" + " \n" + " \tif (rate_change_remuxed)\n" + "@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + " \treturn ret;\n" " }\n" - "=20\n" - "+static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo=\n" - "ng drate,\n" - "+=09=09=09=09=09unsigned long prate)\n" + " \n" + "+static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + "+\t\t\t\t\tunsigned long prate)\n" "+{\n" - "+=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "+=09const struct rockchip_pll_rate_table *rate;\n" - "+=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat=\n" - "e);\n" - "+=09struct regmap *grf =3D rockchip_clk_get_grf();\n" + "+\tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "+\tconst struct rockchip_pll_rate_table *rate;\n" + "+\tunsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);\n" + "+\tstruct regmap *grf = rockchip_clk_get_grf();\n" "+\n" - "+=09if (IS_ERR(grf)) {\n" - "+=09=09pr_debug(\"%s: grf regmap not available, aborting rate change\\n\",=\n" - "\n" - "+=09=09=09 __func__);\n" - "+=09=09return PTR_ERR(grf);\n" - "+=09}\n" + "+\tif (IS_ERR(grf)) {\n" + "+\t\tpr_debug(\"%s: grf regmap not available, aborting rate change\\n\",\n" + "+\t\t\t __func__);\n" + "+\t\treturn PTR_ERR(grf);\n" + "+\t}\n" "+\n" - "+=09pr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu=\n" - "\\n\",\n" - "+=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" + "+\tpr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu\\n\",\n" + "+\t\t __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" "+\n" - "+=09/* Get required rate settings from table */\n" - "+=09rate =3D rockchip_get_pll_settings(pll, drate);\n" - "+=09if (!rate) {\n" - "+=09=09pr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" - "+=09=09=09drate, clk_hw_get_name(hw));\n" - "+=09=09return -EINVAL;\n" - "+=09}\n" + "+\t/* Get required rate settings from table */\n" + "+\trate = rockchip_get_pll_settings(pll, drate);\n" + "+\tif (!rate) {\n" + "+\t\tpr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" + "+\t\t\tdrate, clk_hw_get_name(hw));\n" + "+\t\treturn -EINVAL;\n" + "+\t}\n" "+\n" - "+=09return rockchip_rk3066_pll_set_params(pll, rate);\n" + "+\treturn rockchip_rk3066_pll_set_params(pll, rate);\n" "+}\n" "+\n" " static int rockchip_rk3066_pll_enable(struct clk_hw *hw)\n" " {\n" - " =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw =\n" - "*hw)\n" + " \tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)\n" " {\n" - " =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - " =09const struct rockchip_pll_rate_table *rate;\n" - "-=09unsigned int nf, nr, no, nb;\n" - "+=09struct rockchip_pll_rate_table cur;\n" - " =09unsigned long drate;\n" - "-=09u32 pllcon;\n" - "=20\n" - " =09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" - " =09=09return;\n" - "@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_h=\n" - "w *hw)\n" - " =09if (!rate)\n" - " =09=09return;\n" - "=20\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" - "-=09nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MAS=\n" - "K) + 1;\n" - "-=09no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MAS=\n" - "K) + 1;\n" + " \tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + " \tconst struct rockchip_pll_rate_table *rate;\n" + "-\tunsigned int nf, nr, no, nb;\n" + "+\tstruct rockchip_pll_rate_table cur;\n" + " \tunsigned long drate;\n" + "-\tu32 pllcon;\n" + " \n" + " \tif (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" + " \t\treturn;\n" + "@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)\n" + " \tif (!rate)\n" + " \t\treturn;\n" + " \n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" + "-\tnr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1;\n" + "-\tno = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1;\n" "-\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" - "-=09nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MAS=\n" - "K) + 1;\n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" + "-\tnf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;\n" "-\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" - "-=09nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MAS=\n" - "K) + 1;\n" - "+=09rockchip_rk3066_pll_get_params(pll, &cur);\n" - "=20\n" - " =09pr_debug(\"%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:=\n" - "%d)\\n\",\n" - "-=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, nr,\n" - "-=09=09rate->no, no, rate->nf, nf, rate->nb, nb);\n" - "-=09if (rate->nr !=3D nr || rate->no !=3D no || rate->nf !=3D nf\n" - "-=09=09=09=09=09 || rate->nb !=3D nb) {\n" - "-=09=09struct clk_hw *parent =3D clk_hw_get_parent(hw);\n" - "-=09=09unsigned long prate;\n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" + "-\tnb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MASK) + 1;\n" + "+\trockchip_rk3066_pll_get_params(pll, &cur);\n" + " \n" + " \tpr_debug(\"%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\\n\",\n" + "-\t\t __func__, clk_hw_get_name(hw), drate, rate->nr, nr,\n" + "-\t\trate->no, no, rate->nf, nf, rate->nb, nb);\n" + "-\tif (rate->nr != nr || rate->no != no || rate->nf != nf\n" + "-\t\t\t\t\t || rate->nb != nb) {\n" + "-\t\tstruct clk_hw *parent = clk_hw_get_parent(hw);\n" + "-\t\tunsigned long prate;\n" "-\n" - "-=09=09if (!parent) {\n" - "-=09=09=09pr_warn(\"%s: parent of %s not available\\n\",\n" - "-=09=09=09=09__func__, clk_hw_get_name(hw));\n" - "+=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,\n" - "+=09=09 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);\n" - "+=09if (rate->nr !=3D cur.nr || rate->no !=3D cur.no || rate->nf !=3D c=\n" - "ur.nf\n" - "+=09=09=09=09=09=09 || rate->nb !=3D cur.nb) {\n" - "+=09=09struct regmap *grf =3D rockchip_clk_get_grf();\n" + "-\t\tif (!parent) {\n" + "-\t\t\tpr_warn(\"%s: parent of %s not available\\n\",\n" + "-\t\t\t\t__func__, clk_hw_get_name(hw));\n" + "+\t\t __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,\n" + "+\t\t rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);\n" + "+\tif (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf\n" + "+\t\t\t\t\t\t || rate->nb != cur.nb) {\n" + "+\t\tstruct regmap *grf = rockchip_clk_get_grf();\n" "+\n" - "+=09=09if (IS_ERR(grf))\n" - " =09=09=09return;\n" - "-=09=09}\n" - "=20\n" - " =09=09pr_debug(\"%s: pll %s: rate params do not match rate table, adjus=\n" - "ting\\n\",\n" - " =09=09=09 __func__, clk_hw_get_name(hw));\n" - "-=09=09prate =3D clk_hw_get_rate(parent);\n" - "-=09=09rockchip_rk3066_pll_set_rate(hw, drate, prate);\n" - "+=09=09rockchip_rk3066_pll_set_params(pll, rate);\n" - " =09}\n" + "+\t\tif (IS_ERR(grf))\n" + " \t\t\treturn;\n" + "-\t\t}\n" + " \n" + " \t\tpr_debug(\"%s: pll %s: rate params do not match rate table, adjusting\\n\",\n" + " \t\t\t __func__, clk_hw_get_name(hw));\n" + "-\t\tprate = clk_hw_get_rate(parent);\n" + "-\t\trockchip_rk3066_pll_set_rate(hw, drate, prate);\n" + "+\t\trockchip_rk3066_pll_set_params(pll, rate);\n" + " \t}\n" " }\n" - "=20\n" - "--=20\n" + " \n" + "-- \n" "2.5.3\n" "---------------- 8< --------------------\n" "\n" Heiko -44408a289d889ca3f66fbaa7b6daf0aa2bd33e88ef2b74cf0da22bedc978a36e +46673b69b12c9f5da3d268b72c36da729a34572192c54b38f771bc4089278ee7
diff --git a/a/1.txt b/N2/1.txt index 1c7d6ec..2b0de04 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,19 +1,18 @@ Hi Stephen, Am Dienstag, 22. September 2015, 16:19:00 schrieb Stephen Boyd: -> On 09/23, Heiko St=FCbner wrote: +> On 09/23, Heiko St?bner wrote: > > Am Dienstag, 22. September 2015, 15:41:25 schrieb Stephen Boyd: > > > On 09/17, Xing Zheng wrote: > > > > + > > > > +static void rockchip_rk3036_pll_init(struct clk_hw *hw) -> > >=20 +> > > > > > init ops are "discouraged". Could we do this through assigned > > > rates instead? -> >=20 -> > really? According to Mike that was a valid use-case when we looked = -for an +> > +> > really? According to Mike that was a valid use-case when we looked for an > > initial place for that on the rk3288 :-) . ->=20 +> > A comment in clk.c indicates init ops are discouraged. Maybe this > is a valid use-case on other platforms so it was allowed, but > pretty much every time we see a new init op we have to think @@ -25,54 +24,45 @@ callback!" [0] so it looks like he was convinced of our reasoning at the time :-) . -[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/0= -01570.html +[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/001570.html > > > > +{ -> > > > +=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); -> > > > +=09const struct rockchip_pll_rate_table *rate; -> > > > +=09unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac= -; -> > > > +=09unsigned long drate; -> > > > +=09u32 pllcon; +> > > > + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +> > > > + const struct rockchip_pll_rate_table *rate; +> > > > + unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac; +> > > > + unsigned long drate; +> > > > + u32 pllcon; > > > > + -> > > > +=09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) -> > > > +=09=09return; -> > >=20 -> > > I don't understand what this one does though. This check isn't in= - +> > > > + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) +> > > > + return; +> > > +> > > I don't understand what this one does though. This check isn't in > > > the set rate ops. -> >=20 +> > > > And it shouldn't be :-) -> >=20 -> > The issue this whole thing is trying to solve is aligning the pll s= -ettings +> > +> > The issue this whole thing is trying to solve is aligning the pll settings > > which what we have in the rate table, not what the bootloader set. -> >=20 -> > For example the bootloader could set up a pll at 594MHz with one se= -t of +> > +> > For example the bootloader could set up a pll at 594MHz with one set of > > parameters and after some time - when you don't want to exchange > > bootloaders on shipping devices anymore - it comes to light that a -> > different set of parameters for the same frequency produces for exa= -mple a -> > more stable hdmi signal [I think that was the main reason for the i= -nitial +> > different set of parameters for the same frequency produces for example a +> > more stable hdmi signal [I think that was the main reason for the initial > > change]. -> >=20 -> > So we're not changing the frequency x -> y, which could be easily d= -one +> > +> > So we're not changing the frequency x -> y, which could be easily done > > [and is done already] via assigned-rates, but instead -> >=20 -> > =09x {params a,b,c} -> x {params d,e,f} -> >=20 -> > so the rate itself stays the same, only the frequency generation is= - +> > +> > x {params a,b,c} -> x {params d,e,f} +> > +> > so the rate itself stays the same, only the frequency generation is > > adapted. > Ok. It would be nice if this sort of information was made into a > comment and put in the code. Or at least the commit text for the > change. ->=20 +> > And is there any reason that we need to get the parent clock and > parent rate to align the PLL settings? > It would be nice if we @@ -86,8 +76,7 @@ below actually does work quite nicely on rk3288 boards. ---------------- 8< -------------------- From: Heiko Stuebner <heiko@sntech.de> -Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-cal= -lback +Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-callback Separate the update of pll registers from the actual set_rate function so that the init callback does not need to access clk-API functions. @@ -97,247 +86,216 @@ we can also directly use these new functions in other places too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- - drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++-----------= --------- + drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++------------------- 1 file changed, 74 insertions(+), 61 deletions(-) -diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-= -pll.c +diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 7737a1d..4881eb8 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c -@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip= -_clk_pll *pll) - #define RK3066_PLLCON3_PWRDOWN=09=09(1 << 1) - #define RK3066_PLLCON3_BYPASS=09=09(1 << 0) -=20 -+static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pl= -l, -+=09=09=09=09=09struct rockchip_pll_rate_table *rate) +@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) + #define RK3066_PLLCON3_PWRDOWN (1 << 1) + #define RK3066_PLLCON3_BYPASS (1 << 0) + ++static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, ++ struct rockchip_pll_rate_table *rate) +{ -+=09u32 pllcon; ++ u32 pllcon; + -+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); -+=09rate->nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT) -+=09=09=09=09& RK3066_PLLCON0_NR_MASK) + 1; -+=09rate->no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT) -+=09=09=09=09& RK3066_PLLCON0_OD_MASK) + 1; ++ pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); ++ rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) ++ & RK3066_PLLCON0_NR_MASK) + 1; ++ rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) ++ & RK3066_PLLCON0_OD_MASK) + 1; + -+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); -+=09rate->nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT) -+=09=09=09=09& RK3066_PLLCON1_NF_MASK) + 1; ++ pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); ++ rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) ++ & RK3066_PLLCON1_NF_MASK) + 1; + -+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); -+=09rate->nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT) -+=09=09=09=09& RK3066_PLLCON2_NB_MASK) + 1; ++ pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); ++ rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) ++ & RK3066_PLLCON2_NB_MASK) + 1; +} + - static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw= -, - =09=09=09=09=09=09 unsigned long prate) + static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) { - =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); --=09u64 nf, nr, no, rate64 =3D prate; -+=09struct rockchip_pll_rate_table cur; -+=09u64 rate64 =3D prate; - =09u32 pllcon; -=20 - =09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); -@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_r= -ate(struct clk_hw *hw, - =09=09return prate; - =09} -=20 --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); --=09nf =3D (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK= -; + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +- u64 nf, nr, no, rate64 = prate; ++ struct rockchip_pll_rate_table cur; ++ u64 rate64 = prate; + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); +@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, + return prate; + } + +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); +- nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK; - --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); --=09nr =3D (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK= -; --=09no =3D (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK= -; -+=09rockchip_rk3066_pll_get_params(pll, &cur); -=20 --=09rate64 *=3D (nf + 1); --=09do_div(rate64, nr + 1); --=09do_div(rate64, no + 1); -+=09rate64 *=3D cur.nf; -+=09do_div(rate64, cur.nr); -+=09do_div(rate64, cur.no); -=20 - =09return (unsigned long)rate64; +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); +- nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK; +- no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK; ++ rockchip_rk3066_pll_get_params(pll, &cur); + +- rate64 *= (nf + 1); +- do_div(rate64, nr + 1); +- do_div(rate64, no + 1); ++ rate64 *= cur.nf; ++ do_div(rate64, cur.nr); ++ do_div(rate64, cur.no); + + return (unsigned long)rate64; } -=20 --static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo= -ng drate, --=09=09=09=09=09unsigned long prate) -+static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll= -, -+=09=09=09=09const struct rockchip_pll_rate_table *rate) + +-static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, +- unsigned long prate) ++static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, ++ const struct rockchip_pll_rate_table *rate) { --=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); --=09const struct rockchip_pll_rate_table *rate; --=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat= -e); --=09struct regmap *grf =3D rockchip_clk_get_grf(); --=09struct clk_mux *pll_mux =3D &pll->pll_mux; - =09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops; -+=09struct clk_mux *pll_mux =3D &pll->pll_mux; -+=09struct rockchip_pll_rate_table cur; - =09int rate_change_remuxed =3D 0; - =09int cur_parent; - =09int ret; -=20 --=09if (IS_ERR(grf)) { --=09=09pr_debug("%s: grf regmap not available, aborting rate change\n",= - --=09=09=09 __func__); --=09=09return PTR_ERR(grf); --=09} +- struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +- const struct rockchip_pll_rate_table *rate; +- unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); +- struct regmap *grf = rockchip_clk_get_grf(); +- struct clk_mux *pll_mux = &pll->pll_mux; + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; ++ struct clk_mux *pll_mux = &pll->pll_mux; ++ struct rockchip_pll_rate_table cur; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + +- if (IS_ERR(grf)) { +- pr_debug("%s: grf regmap not available, aborting rate change\n", +- __func__); +- return PTR_ERR(grf); +- } - --=09pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu= -\n", --=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate); +- pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", +- __func__, clk_hw_get_name(hw), old_rate, drate, prate); - --=09/* Get required rate settings from table */ --=09rate =3D rockchip_get_pll_settings(pll, drate); --=09if (!rate) { --=09=09pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, --=09=09=09drate, clk_hw_get_name(hw)); --=09=09return -EINVAL; --=09} +- /* Get required rate settings from table */ +- rate = rockchip_get_pll_settings(pll, drate); +- if (!rate) { +- pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, +- drate, clk_hw_get_name(hw)); +- return -EINVAL; +- } - - =09pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", - =09=09 __func__, rate->rate, rate->nr, rate->no, rate->nf); -=20 -+=09rockchip_rk3066_pll_get_params(pll, &cur); -+=09cur.rate =3D 0; + pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", + __func__, rate->rate, rate->nr, rate->no, rate->nf); + ++ rockchip_rk3066_pll_get_params(pll, &cur); ++ cur.rate = 0; + - =09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); - =09if (cur_parent =3D=3D PLL_MODE_NORM) { - =09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); -@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_= -hw *hw, unsigned long drate, - =09/* wait for the pll to lock */ - =09ret =3D rockchip_pll_wait_lock(pll); - =09if (ret) { --=09=09pr_warn("%s: pll did not lock, trying to restore old rate %lu\n"= -, --=09=09=09__func__, old_rate); --=09=09rockchip_rk3066_pll_set_rate(hw, old_rate, prate); -+=09=09pr_warn("%s: pll update unsucessful, trying to restore old param= -s\n", -+=09=09=09__func__); -+=09=09rockchip_rk3066_pll_set_params(pll, &cur); - =09} -=20 - =09if (rate_change_remuxed) -@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk= -_hw *hw, unsigned long drate, - =09return ret; + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); +@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, + /* wait for the pll to lock */ + ret = rockchip_pll_wait_lock(pll); + if (ret) { +- pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", +- __func__, old_rate); +- rockchip_rk3066_pll_set_rate(hw, old_rate, prate); ++ pr_warn("%s: pll update unsucessful, trying to restore old params\n", ++ __func__); ++ rockchip_rk3066_pll_set_params(pll, &cur); + } + + if (rate_change_remuxed) +@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, + return ret; } -=20 -+static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo= -ng drate, -+=09=09=09=09=09unsigned long prate) + ++static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, ++ unsigned long prate) +{ -+=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); -+=09const struct rockchip_pll_rate_table *rate; -+=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat= -e); -+=09struct regmap *grf =3D rockchip_clk_get_grf(); ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ const struct rockchip_pll_rate_table *rate; ++ unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); ++ struct regmap *grf = rockchip_clk_get_grf(); + -+=09if (IS_ERR(grf)) { -+=09=09pr_debug("%s: grf regmap not available, aborting rate change\n",= - -+=09=09=09 __func__); -+=09=09return PTR_ERR(grf); -+=09} ++ if (IS_ERR(grf)) { ++ pr_debug("%s: grf regmap not available, aborting rate change\n", ++ __func__); ++ return PTR_ERR(grf); ++ } + -+=09pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu= -\n", -+=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate); ++ pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", ++ __func__, clk_hw_get_name(hw), old_rate, drate, prate); + -+=09/* Get required rate settings from table */ -+=09rate =3D rockchip_get_pll_settings(pll, drate); -+=09if (!rate) { -+=09=09pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, -+=09=09=09drate, clk_hw_get_name(hw)); -+=09=09return -EINVAL; -+=09} ++ /* Get required rate settings from table */ ++ rate = rockchip_get_pll_settings(pll, drate); ++ if (!rate) { ++ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, ++ drate, clk_hw_get_name(hw)); ++ return -EINVAL; ++ } + -+=09return rockchip_rk3066_pll_set_params(pll, rate); ++ return rockchip_rk3066_pll_set_params(pll, rate); +} + static int rockchip_rk3066_pll_enable(struct clk_hw *hw) { - =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); -@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw = -*hw) + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); +@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) { - =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw); - =09const struct rockchip_pll_rate_table *rate; --=09unsigned int nf, nr, no, nb; -+=09struct rockchip_pll_rate_table cur; - =09unsigned long drate; --=09u32 pllcon; -=20 - =09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) - =09=09return; -@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_h= -w *hw) - =09if (!rate) - =09=09return; -=20 --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); --=09nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MAS= -K) + 1; --=09no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MAS= -K) + 1; + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; +- unsigned int nf, nr, no, nb; ++ struct rockchip_pll_rate_table cur; + unsigned long drate; +- u32 pllcon; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return; +@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) + if (!rate) + return; + +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); +- nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1; +- no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1; - --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); --=09nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MAS= -K) + 1; +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); +- nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1; - --=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); --=09nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MAS= -K) + 1; -+=09rockchip_rk3066_pll_get_params(pll, &cur); -=20 - =09pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:= -%d)\n", --=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, nr, --=09=09rate->no, no, rate->nf, nf, rate->nb, nb); --=09if (rate->nr !=3D nr || rate->no !=3D no || rate->nf !=3D nf --=09=09=09=09=09 || rate->nb !=3D nb) { --=09=09struct clk_hw *parent =3D clk_hw_get_parent(hw); --=09=09unsigned long prate; +- pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); +- nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MASK) + 1; ++ rockchip_rk3066_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", +- __func__, clk_hw_get_name(hw), drate, rate->nr, nr, +- rate->no, no, rate->nf, nf, rate->nb, nb); +- if (rate->nr != nr || rate->no != no || rate->nf != nf +- || rate->nb != nb) { +- struct clk_hw *parent = clk_hw_get_parent(hw); +- unsigned long prate; - --=09=09if (!parent) { --=09=09=09pr_warn("%s: parent of %s not available\n", --=09=09=09=09__func__, clk_hw_get_name(hw)); -+=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, -+=09=09 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); -+=09if (rate->nr !=3D cur.nr || rate->no !=3D cur.no || rate->nf !=3D c= -ur.nf -+=09=09=09=09=09=09 || rate->nb !=3D cur.nb) { -+=09=09struct regmap *grf =3D rockchip_clk_get_grf(); +- if (!parent) { +- pr_warn("%s: parent of %s not available\n", +- __func__, clk_hw_get_name(hw)); ++ __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, ++ rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); ++ if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf ++ || rate->nb != cur.nb) { ++ struct regmap *grf = rockchip_clk_get_grf(); + -+=09=09if (IS_ERR(grf)) - =09=09=09return; --=09=09} -=20 - =09=09pr_debug("%s: pll %s: rate params do not match rate table, adjus= -ting\n", - =09=09=09 __func__, clk_hw_get_name(hw)); --=09=09prate =3D clk_hw_get_rate(parent); --=09=09rockchip_rk3066_pll_set_rate(hw, drate, prate); -+=09=09rockchip_rk3066_pll_set_params(pll, rate); - =09} ++ if (IS_ERR(grf)) + return; +- } + + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); +- prate = clk_hw_get_rate(parent); +- rockchip_rk3066_pll_set_rate(hw, drate, prate); ++ rockchip_rk3066_pll_set_params(pll, rate); + } } -=20 ---=20 + +-- 2.5.3 ---------------- 8< -------------------- diff --git a/a/content_digest b/N2/content_digest index 1b2b05a..f363105 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,34 +1,27 @@ "ref\01442478540-15068-1-git-send-email-zhengxing@rock-chips.com\0" "ref\02850967.rjRj3AZerS@diego\0" "ref\020150922231900.GL23081@codeaurora.org\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH v2 4/9] clk: rockchip: add new clock type and controller for rk3036\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "Subject\0[PATCH v2 4/9] clk: rockchip: add new clock type and controller for rk3036\0" "Date\0Thu, 01 Oct 2015 01:32:19 +0200\0" - "To\0Stephen Boyd <sboyd@codeaurora.org>\0" - "Cc\0Xing Zheng <zhengxing@rock-chips.com>" - linux-rockchip@lists.infradead.org - Michael Turquette <mturquette@baylibre.com> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Stephen,\n" "\n" "Am Dienstag, 22. September 2015, 16:19:00 schrieb Stephen Boyd:\n" - "> On 09/23, Heiko St=FCbner wrote:\n" + "> On 09/23, Heiko St?bner wrote:\n" "> > Am Dienstag, 22. September 2015, 15:41:25 schrieb Stephen Boyd:\n" "> > > On 09/17, Xing Zheng wrote:\n" "> > > > +\n" "> > > > +static void rockchip_rk3036_pll_init(struct clk_hw *hw)\n" - "> > >=20\n" + "> > > \n" "> > > init ops are \"discouraged\". Could we do this through assigned\n" "> > > rates instead?\n" - "> >=20\n" - "> > really? According to Mike that was a valid use-case when we looked =\n" - "for an\n" + "> > \n" + "> > really? According to Mike that was a valid use-case when we looked for an\n" "> > initial place for that on the rk3288 :-) .\n" - ">=20\n" + "> \n" "> A comment in clk.c indicates init ops are discouraged. Maybe this\n" "> is a valid use-case on other platforms so it was allowed, but\n" "> pretty much every time we see a new init op we have to think\n" @@ -40,54 +33,45 @@ "so it looks like he was convinced of our reasoning at the time :-) .\n" "\n" "\n" - "[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/0=\n" - "01570.html\n" + "[0] http://lists.infradead.org/pipermail/linux-rockchip/2014-November/001570.html\n" "\n" "\n" "> > > > +{\n" - "> > > > +=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "> > > > +=09const struct rockchip_pll_rate_table *rate;\n" - "> > > > +=09unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac=\n" - ";\n" - "> > > > +=09unsigned long drate;\n" - "> > > > +=09u32 pllcon;\n" + "> > > > +\tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "> > > > +\tconst struct rockchip_pll_rate_table *rate;\n" + "> > > > +\tunsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac;\n" + "> > > > +\tunsigned long drate;\n" + "> > > > +\tu32 pllcon;\n" "> > > > +\n" - "> > > > +=09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" - "> > > > +=09=09return;\n" - "> > >=20\n" - "> > > I don't understand what this one does though. This check isn't in=\n" - "\n" + "> > > > +\tif (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" + "> > > > +\t\treturn;\n" + "> > > \n" + "> > > I don't understand what this one does though. This check isn't in\n" "> > > the set rate ops.\n" - "> >=20\n" + "> > \n" "> > And it shouldn't be :-)\n" - "> >=20\n" - "> > The issue this whole thing is trying to solve is aligning the pll s=\n" - "ettings\n" + "> > \n" + "> > The issue this whole thing is trying to solve is aligning the pll settings\n" "> > which what we have in the rate table, not what the bootloader set.\n" - "> >=20\n" - "> > For example the bootloader could set up a pll at 594MHz with one se=\n" - "t of\n" + "> > \n" + "> > For example the bootloader could set up a pll at 594MHz with one set of\n" "> > parameters and after some time - when you don't want to exchange\n" "> > bootloaders on shipping devices anymore - it comes to light that a\n" - "> > different set of parameters for the same frequency produces for exa=\n" - "mple a\n" - "> > more stable hdmi signal [I think that was the main reason for the i=\n" - "nitial\n" + "> > different set of parameters for the same frequency produces for example a\n" + "> > more stable hdmi signal [I think that was the main reason for the initial\n" "> > change].\n" - "> >=20\n" - "> > So we're not changing the frequency x -> y, which could be easily d=\n" - "one\n" + "> > \n" + "> > So we're not changing the frequency x -> y, which could be easily done\n" "> > [and is done already] via assigned-rates, but instead\n" - "> >=20\n" - "> > =09x {params a,b,c} -> x {params d,e,f}\n" - "> >=20\n" - "> > so the rate itself stays the same, only the frequency generation is=\n" - "\n" + "> > \n" + "> > \tx {params a,b,c} -> x {params d,e,f}\n" + "> > \n" + "> > so the rate itself stays the same, only the frequency generation is\n" "> > adapted.\n" "> Ok. It would be nice if this sort of information was made into a\n" "> comment and put in the code. Or at least the commit text for the\n" "> change.\n" - ">=20\n" + "> \n" "> And is there any reason that we need to get the parent clock and\n" "> parent rate to align the PLL settings?\n" "> It would be nice if we\n" @@ -101,8 +85,7 @@ "\n" "---------------- 8< --------------------\n" "From: Heiko Stuebner <heiko@sntech.de>\n" - "Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-cal=\n" - "lback\n" + "Subject: [PATCH] clk: rockchip: don't use clk_ APIs in the pll init-callback\n" "\n" "Separate the update of pll registers from the actual set_rate function\n" "so that the init callback does not need to access clk-API functions.\n" @@ -112,250 +95,219 @@ "\n" "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" "---\n" - " drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++-----------=\n" - "--------\n" + " drivers/clk/rockchip/clk-pll.c | 135 ++++++++++++++++++++++-------------------\n" " 1 file changed, 74 insertions(+), 61 deletions(-)\n" "\n" - "diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-=\n" - "pll.c\n" + "diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c\n" "index 7737a1d..4881eb8 100644\n" "--- a/drivers/clk/rockchip/clk-pll.c\n" "+++ b/drivers/clk/rockchip/clk-pll.c\n" - "@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip=\n" - "_clk_pll *pll)\n" - " #define RK3066_PLLCON3_PWRDOWN=09=09(1 << 1)\n" - " #define RK3066_PLLCON3_BYPASS=09=09(1 << 0)\n" - "=20\n" - "+static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pl=\n" - "l,\n" - "+=09=09=09=09=09struct rockchip_pll_rate_table *rate)\n" + "@@ -126,11 +126,32 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)\n" + " #define RK3066_PLLCON3_PWRDOWN\t\t(1 << 1)\n" + " #define RK3066_PLLCON3_BYPASS\t\t(1 << 0)\n" + " \n" + "+static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,\n" + "+\t\t\t\t\tstruct rockchip_pll_rate_table *rate)\n" "+{\n" - "+=09u32 pllcon;\n" + "+\tu32 pllcon;\n" "+\n" - "+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" - "+=09rate->nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON0_NR_MASK) + 1;\n" - "+=09rate->no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON0_OD_MASK) + 1;\n" + "+\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" + "+\trate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON0_NR_MASK) + 1;\n" + "+\trate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON0_OD_MASK) + 1;\n" "+\n" - "+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" - "+=09rate->nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON1_NF_MASK) + 1;\n" + "+\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" + "+\trate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON1_NF_MASK) + 1;\n" "+\n" - "+=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" - "+=09rate->nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT)\n" - "+=09=09=09=09& RK3066_PLLCON2_NB_MASK) + 1;\n" + "+\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" + "+\trate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)\n" + "+\t\t\t\t& RK3066_PLLCON2_NB_MASK) + 1;\n" "+}\n" "+\n" - " static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw=\n" - ",\n" - " =09=09=09=09=09=09 unsigned long prate)\n" + " static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,\n" + " \t\t\t\t\t\t unsigned long prate)\n" " {\n" - " =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "-=09u64 nf, nr, no, rate64 =3D prate;\n" - "+=09struct rockchip_pll_rate_table cur;\n" - "+=09u64 rate64 =3D prate;\n" - " =09u32 pllcon;\n" - "=20\n" - " =09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(3));\n" - "@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_r=\n" - "ate(struct clk_hw *hw,\n" - " =09=09return prate;\n" - " =09}\n" - "=20\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" - "-=09nf =3D (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK=\n" - ";\n" + " \tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "-\tu64 nf, nr, no, rate64 = prate;\n" + "+\tstruct rockchip_pll_rate_table cur;\n" + "+\tu64 rate64 = prate;\n" + " \tu32 pllcon;\n" + " \n" + " \tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));\n" + "@@ -140,53 +161,31 @@ static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,\n" + " \t\treturn prate;\n" + " \t}\n" + " \n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" + "-\tnf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK;\n" "-\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" - "-=09nr =3D (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK=\n" - ";\n" - "-=09no =3D (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK=\n" - ";\n" - "+=09rockchip_rk3066_pll_get_params(pll, &cur);\n" - "=20\n" - "-=09rate64 *=3D (nf + 1);\n" - "-=09do_div(rate64, nr + 1);\n" - "-=09do_div(rate64, no + 1);\n" - "+=09rate64 *=3D cur.nf;\n" - "+=09do_div(rate64, cur.nr);\n" - "+=09do_div(rate64, cur.no);\n" - "=20\n" - " =09return (unsigned long)rate64;\n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" + "-\tnr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK;\n" + "-\tno = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK;\n" + "+\trockchip_rk3066_pll_get_params(pll, &cur);\n" + " \n" + "-\trate64 *= (nf + 1);\n" + "-\tdo_div(rate64, nr + 1);\n" + "-\tdo_div(rate64, no + 1);\n" + "+\trate64 *= cur.nf;\n" + "+\tdo_div(rate64, cur.nr);\n" + "+\tdo_div(rate64, cur.no);\n" + " \n" + " \treturn (unsigned long)rate64;\n" " }\n" - "=20\n" - "-static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo=\n" - "ng drate,\n" - "-=09=09=09=09=09unsigned long prate)\n" - "+static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll=\n" - ",\n" - "+=09=09=09=09const struct rockchip_pll_rate_table *rate)\n" + " \n" + "-static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + "-\t\t\t\t\tunsigned long prate)\n" + "+static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,\n" + "+\t\t\t\tconst struct rockchip_pll_rate_table *rate)\n" " {\n" - "-=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "-=09const struct rockchip_pll_rate_table *rate;\n" - "-=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat=\n" - "e);\n" - "-=09struct regmap *grf =3D rockchip_clk_get_grf();\n" - "-=09struct clk_mux *pll_mux =3D &pll->pll_mux;\n" - " =09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops;\n" - "+=09struct clk_mux *pll_mux =3D &pll->pll_mux;\n" - "+=09struct rockchip_pll_rate_table cur;\n" - " =09int rate_change_remuxed =3D 0;\n" - " =09int cur_parent;\n" - " =09int ret;\n" - "=20\n" - "-=09if (IS_ERR(grf)) {\n" - "-=09=09pr_debug(\"%s: grf regmap not available, aborting rate change\\n\",=\n" - "\n" - "-=09=09=09 __func__);\n" - "-=09=09return PTR_ERR(grf);\n" - "-=09}\n" + "-\tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "-\tconst struct rockchip_pll_rate_table *rate;\n" + "-\tunsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);\n" + "-\tstruct regmap *grf = rockchip_clk_get_grf();\n" + "-\tstruct clk_mux *pll_mux = &pll->pll_mux;\n" + " \tconst struct clk_ops *pll_mux_ops = pll->pll_mux_ops;\n" + "+\tstruct clk_mux *pll_mux = &pll->pll_mux;\n" + "+\tstruct rockchip_pll_rate_table cur;\n" + " \tint rate_change_remuxed = 0;\n" + " \tint cur_parent;\n" + " \tint ret;\n" + " \n" + "-\tif (IS_ERR(grf)) {\n" + "-\t\tpr_debug(\"%s: grf regmap not available, aborting rate change\\n\",\n" + "-\t\t\t __func__);\n" + "-\t\treturn PTR_ERR(grf);\n" + "-\t}\n" "-\n" - "-=09pr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu=\n" - "\\n\",\n" - "-=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" + "-\tpr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu\\n\",\n" + "-\t\t __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" "-\n" - "-=09/* Get required rate settings from table */\n" - "-=09rate =3D rockchip_get_pll_settings(pll, drate);\n" - "-=09if (!rate) {\n" - "-=09=09pr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" - "-=09=09=09drate, clk_hw_get_name(hw));\n" - "-=09=09return -EINVAL;\n" - "-=09}\n" + "-\t/* Get required rate settings from table */\n" + "-\trate = rockchip_get_pll_settings(pll, drate);\n" + "-\tif (!rate) {\n" + "-\t\tpr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" + "-\t\t\tdrate, clk_hw_get_name(hw));\n" + "-\t\treturn -EINVAL;\n" + "-\t}\n" "-\n" - " =09pr_debug(\"%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\\n\",\n" - " =09=09 __func__, rate->rate, rate->nr, rate->no, rate->nf);\n" - "=20\n" - "+=09rockchip_rk3066_pll_get_params(pll, &cur);\n" - "+=09cur.rate =3D 0;\n" + " \tpr_debug(\"%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\\n\",\n" + " \t\t __func__, rate->rate, rate->nr, rate->no, rate->nf);\n" + " \n" + "+\trockchip_rk3066_pll_get_params(pll, &cur);\n" + "+\tcur.rate = 0;\n" "+\n" - " =09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw);\n" - " =09if (cur_parent =3D=3D PLL_MODE_NORM) {\n" - " =09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" - "@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_=\n" - "hw *hw, unsigned long drate,\n" - " =09/* wait for the pll to lock */\n" - " =09ret =3D rockchip_pll_wait_lock(pll);\n" - " =09if (ret) {\n" - "-=09=09pr_warn(\"%s: pll did not lock, trying to restore old rate %lu\\n\"=\n" - ",\n" - "-=09=09=09__func__, old_rate);\n" - "-=09=09rockchip_rk3066_pll_set_rate(hw, old_rate, prate);\n" - "+=09=09pr_warn(\"%s: pll update unsucessful, trying to restore old param=\n" - "s\\n\",\n" - "+=09=09=09__func__);\n" - "+=09=09rockchip_rk3066_pll_set_params(pll, &cur);\n" - " =09}\n" - "=20\n" - " =09if (rate_change_remuxed)\n" - "@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk=\n" - "_hw *hw, unsigned long drate,\n" - " =09return ret;\n" + " \tcur_parent = pll_mux_ops->get_parent(&pll_mux->hw);\n" + " \tif (cur_parent == PLL_MODE_NORM) {\n" + " \t\tpll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" + "@@ -219,9 +218,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + " \t/* wait for the pll to lock */\n" + " \tret = rockchip_pll_wait_lock(pll);\n" + " \tif (ret) {\n" + "-\t\tpr_warn(\"%s: pll did not lock, trying to restore old rate %lu\\n\",\n" + "-\t\t\t__func__, old_rate);\n" + "-\t\trockchip_rk3066_pll_set_rate(hw, old_rate, prate);\n" + "+\t\tpr_warn(\"%s: pll update unsucessful, trying to restore old params\\n\",\n" + "+\t\t\t__func__);\n" + "+\t\trockchip_rk3066_pll_set_params(pll, &cur);\n" + " \t}\n" + " \n" + " \tif (rate_change_remuxed)\n" + "@@ -230,6 +229,34 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + " \treturn ret;\n" " }\n" - "=20\n" - "+static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned lo=\n" - "ng drate,\n" - "+=09=09=09=09=09unsigned long prate)\n" + " \n" + "+static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,\n" + "+\t\t\t\t\tunsigned long prate)\n" "+{\n" - "+=09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "+=09const struct rockchip_pll_rate_table *rate;\n" - "+=09unsigned long old_rate =3D rockchip_rk3066_pll_recalc_rate(hw, prat=\n" - "e);\n" - "+=09struct regmap *grf =3D rockchip_clk_get_grf();\n" + "+\tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "+\tconst struct rockchip_pll_rate_table *rate;\n" + "+\tunsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);\n" + "+\tstruct regmap *grf = rockchip_clk_get_grf();\n" "+\n" - "+=09if (IS_ERR(grf)) {\n" - "+=09=09pr_debug(\"%s: grf regmap not available, aborting rate change\\n\",=\n" - "\n" - "+=09=09=09 __func__);\n" - "+=09=09return PTR_ERR(grf);\n" - "+=09}\n" + "+\tif (IS_ERR(grf)) {\n" + "+\t\tpr_debug(\"%s: grf regmap not available, aborting rate change\\n\",\n" + "+\t\t\t __func__);\n" + "+\t\treturn PTR_ERR(grf);\n" + "+\t}\n" "+\n" - "+=09pr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu=\n" - "\\n\",\n" - "+=09=09 __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" + "+\tpr_debug(\"%s: changing %s from %lu to %lu with a parent rate of %lu\\n\",\n" + "+\t\t __func__, clk_hw_get_name(hw), old_rate, drate, prate);\n" "+\n" - "+=09/* Get required rate settings from table */\n" - "+=09rate =3D rockchip_get_pll_settings(pll, drate);\n" - "+=09if (!rate) {\n" - "+=09=09pr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" - "+=09=09=09drate, clk_hw_get_name(hw));\n" - "+=09=09return -EINVAL;\n" - "+=09}\n" + "+\t/* Get required rate settings from table */\n" + "+\trate = rockchip_get_pll_settings(pll, drate);\n" + "+\tif (!rate) {\n" + "+\t\tpr_err(\"%s: Invalid rate : %lu for pll clk %s\\n\", __func__,\n" + "+\t\t\tdrate, clk_hw_get_name(hw));\n" + "+\t\treturn -EINVAL;\n" + "+\t}\n" "+\n" - "+=09return rockchip_rk3066_pll_set_params(pll, rate);\n" + "+\treturn rockchip_rk3066_pll_set_params(pll, rate);\n" "+}\n" "+\n" " static int rockchip_rk3066_pll_enable(struct clk_hw *hw)\n" " {\n" - " =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - "@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw =\n" - "*hw)\n" + " \tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + "@@ -261,9 +288,8 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)\n" " {\n" - " =09struct rockchip_clk_pll *pll =3D to_rockchip_clk_pll(hw);\n" - " =09const struct rockchip_pll_rate_table *rate;\n" - "-=09unsigned int nf, nr, no, nb;\n" - "+=09struct rockchip_pll_rate_table cur;\n" - " =09unsigned long drate;\n" - "-=09u32 pllcon;\n" - "=20\n" - " =09if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" - " =09=09return;\n" - "@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_h=\n" - "w *hw)\n" - " =09if (!rate)\n" - " =09=09return;\n" - "=20\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" - "-=09nr =3D ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MAS=\n" - "K) + 1;\n" - "-=09no =3D ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MAS=\n" - "K) + 1;\n" + " \tstruct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);\n" + " \tconst struct rockchip_pll_rate_table *rate;\n" + "-\tunsigned int nf, nr, no, nb;\n" + "+\tstruct rockchip_pll_rate_table cur;\n" + " \tunsigned long drate;\n" + "-\tu32 pllcon;\n" + " \n" + " \tif (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))\n" + " \t\treturn;\n" + "@@ -275,34 +301,21 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)\n" + " \tif (!rate)\n" + " \t\treturn;\n" + " \n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));\n" + "-\tnr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1;\n" + "-\tno = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1;\n" "-\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" - "-=09nf =3D ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MAS=\n" - "K) + 1;\n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));\n" + "-\tnf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;\n" "-\n" - "-=09pllcon =3D readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" - "-=09nb =3D ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MAS=\n" - "K) + 1;\n" - "+=09rockchip_rk3066_pll_get_params(pll, &cur);\n" - "=20\n" - " =09pr_debug(\"%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:=\n" - "%d)\\n\",\n" - "-=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, nr,\n" - "-=09=09rate->no, no, rate->nf, nf, rate->nb, nb);\n" - "-=09if (rate->nr !=3D nr || rate->no !=3D no || rate->nf !=3D nf\n" - "-=09=09=09=09=09 || rate->nb !=3D nb) {\n" - "-=09=09struct clk_hw *parent =3D clk_hw_get_parent(hw);\n" - "-=09=09unsigned long prate;\n" + "-\tpllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));\n" + "-\tnb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MASK) + 1;\n" + "+\trockchip_rk3066_pll_get_params(pll, &cur);\n" + " \n" + " \tpr_debug(\"%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\\n\",\n" + "-\t\t __func__, clk_hw_get_name(hw), drate, rate->nr, nr,\n" + "-\t\trate->no, no, rate->nf, nf, rate->nb, nb);\n" + "-\tif (rate->nr != nr || rate->no != no || rate->nf != nf\n" + "-\t\t\t\t\t || rate->nb != nb) {\n" + "-\t\tstruct clk_hw *parent = clk_hw_get_parent(hw);\n" + "-\t\tunsigned long prate;\n" "-\n" - "-=09=09if (!parent) {\n" - "-=09=09=09pr_warn(\"%s: parent of %s not available\\n\",\n" - "-=09=09=09=09__func__, clk_hw_get_name(hw));\n" - "+=09=09 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,\n" - "+=09=09 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);\n" - "+=09if (rate->nr !=3D cur.nr || rate->no !=3D cur.no || rate->nf !=3D c=\n" - "ur.nf\n" - "+=09=09=09=09=09=09 || rate->nb !=3D cur.nb) {\n" - "+=09=09struct regmap *grf =3D rockchip_clk_get_grf();\n" + "-\t\tif (!parent) {\n" + "-\t\t\tpr_warn(\"%s: parent of %s not available\\n\",\n" + "-\t\t\t\t__func__, clk_hw_get_name(hw));\n" + "+\t\t __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,\n" + "+\t\t rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);\n" + "+\tif (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf\n" + "+\t\t\t\t\t\t || rate->nb != cur.nb) {\n" + "+\t\tstruct regmap *grf = rockchip_clk_get_grf();\n" "+\n" - "+=09=09if (IS_ERR(grf))\n" - " =09=09=09return;\n" - "-=09=09}\n" - "=20\n" - " =09=09pr_debug(\"%s: pll %s: rate params do not match rate table, adjus=\n" - "ting\\n\",\n" - " =09=09=09 __func__, clk_hw_get_name(hw));\n" - "-=09=09prate =3D clk_hw_get_rate(parent);\n" - "-=09=09rockchip_rk3066_pll_set_rate(hw, drate, prate);\n" - "+=09=09rockchip_rk3066_pll_set_params(pll, rate);\n" - " =09}\n" + "+\t\tif (IS_ERR(grf))\n" + " \t\t\treturn;\n" + "-\t\t}\n" + " \n" + " \t\tpr_debug(\"%s: pll %s: rate params do not match rate table, adjusting\\n\",\n" + " \t\t\t __func__, clk_hw_get_name(hw));\n" + "-\t\tprate = clk_hw_get_rate(parent);\n" + "-\t\trockchip_rk3066_pll_set_rate(hw, drate, prate);\n" + "+\t\trockchip_rk3066_pll_set_params(pll, rate);\n" + " \t}\n" " }\n" - "=20\n" - "--=20\n" + " \n" + "-- \n" "2.5.3\n" "---------------- 8< --------------------\n" "\n" Heiko -44408a289d889ca3f66fbaa7b6daf0aa2bd33e88ef2b74cf0da22bedc978a36e +7cb8029270fea8a2f550eba96c98cf678a3012bc8002e4268e6b43f038a84638
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