Russell,

Please review and consider for inclusion, the following patch for the 
Marvell MultiProtocol Serial Controller (MPSC).  This ctlr is on a 
series of host bridges (and other things) for PPC and MIPS processors.

I tried to design the driver to keep the processor/platform-specific 
code out of the main driver code.  I made an additional file for ppc32 
specific code.  If/when someone with a mips platform wants to use it, 
they can create a mpsc_mips file.

The ctlr operates similar to a typical network controller with send and 
receive rings.  Unfortunately there are many errata so you will see some 
"unusual" things in the code.  For example:
a) An erratum prevents the reading of several registers on the ctlr 
(writing is okay).  To work around that, a local copy of what the 
registers are is kept and special macros are used to access those 
mirrored values.
b) Another erratum says that the MPSC cannot be used to access cache 
coherent memory (and all of the systems I use are coherent).  However, 
it seems to work okay as long as there are no snoop hits so there are 
macros in the code to manually manage the caches to prevent snoop hits.  
Each macro checks a flag to see if the manual cache mgmt is necessary as 
not all versions have the erratum.

The driver seems to work well but more testing is needed and it is 
lacking KGDB support.  I will get to both of those in time.

One final thing, I need a minor number assignment for the 204 major 
(Low-density serial ports).  How do I do that?  (I'm using 5 as a place 
holder.)

Thank you,

Mark
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