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From: Arrigo Benedetti <arrigo@vision.caltech.edu>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev list <linuxppc-dev@ozlabs.org>
Subject: Re: Disabling interrupts on a SMP system
Date: Fri, 29 Oct 2004 10:32:09 -0700	[thread overview]
Message-ID: <41827E99.1090206@vision.caltech.edu> (raw)
In-Reply-To: <1099011090.29689.96.camel@gaston>

Benjamin Herrenschmidt wrote:

>On Thu, 2004-10-28 at 16:58 -0700, Arrigo Benedetti wrote:
>
>  
>
>>To achieve real-time performance in a very critical section of code. 
>>Even after moving all the
>>interrupts to CPU0, there are still two interrupts running on CPU1 that 
>>are disturbing the
>>execution of the time-critical code:
>>    
>>
>
>  
>
>>118:         15      21134   OpenPIC   Level     IPI0 (call function)
>>119:        888        904   OpenPIC   Level     IPI1 (reschedule)
>>    
>>
>
>Those are normal, they are cross-CPU interrupts used internally by the
>kernel. There are also non-visible in that list the timer interrupts on
>both CPUs. You just can't do anything against these.
>
>  
>

Have these interrupts anything to do with the load balancer? I have 
disabled the load balancer code
in linux/sched.c (just commented out all the code in load_balance()).
Maybe the only solution is to write a kernel module?

-Arrigo

  parent reply	other threads:[~2004-10-29 17:32 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-10-28 21:45 Disabling interrupts on a SMP system Arrigo Benedetti
2004-10-28 23:39 ` Benjamin Herrenschmidt
2004-10-28 23:58   ` Arrigo Benedetti
2004-10-29  0:51     ` Benjamin Herrenschmidt
2004-10-29 10:10       ` Gabriel Paubert
2004-10-29 23:00         ` Benjamin Herrenschmidt
2004-11-03 12:30           ` Gabriel Paubert
2004-11-03 22:11             ` Benjamin Herrenschmidt
2004-11-04 12:57               ` Gabriel Paubert
2004-11-15 11:55               ` Gabriel Paubert
2004-10-29 17:32       ` Arrigo Benedetti [this message]
2004-10-29 23:11         ` Benjamin Herrenschmidt

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