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From: Peter Asemann <peter.asemann@web.de>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] CFG_HZ and CFG_SCCR question
Date: Wed, 08 Dec 2004 16:39:25 +0100	[thread overview]
Message-ID: <41B7202D.9070508@web.de> (raw)

1. There is a CFG_HZ configuration setting in many config files, but 
it's not mentioned in the README.
The source code of components where it is used suggests it has to do 
with timer issues.

Having thought and done some "research" on that matter I do believe now 
that the CFG_HZ setting must have something to do with the expiry of 
some timer, but probably doesn't set the tmbclk/tbclk but some counter 
to have some timer expire every CFG_HZ times per second. Is that right?

2. Whilst taking a look in the MPC875 documentation I found there are 
system registers I'd like to take influence on to make sure there are 
the "right" values in them. For example the SCCR. I saw that in the 
README SCCR is mentioned:

- CFG_SCCR:     System Clock and reset Control Register (15-27)

So I suppose by defining CFG_SCCR as something I assign the value of 
something to the register and therefore set the registers content.

But what do the numbers (the range?) in the braces mean?

Best regards and thanks for reading,

Peter Asemann

             reply	other threads:[~2004-12-08 15:39 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-12-08 15:39 Peter Asemann [this message]
2004-12-08 16:14 ` [U-Boot-Users] CFG_HZ and CFG_SCCR question Wolfgang Denk

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