[U-Boot-Users] Re: One more step to conclude the u-boot port to pxa255 board

[Seido Nakanishi <lista@topcomm.com.br>]

Hello,

We are just finnishing the port of u-boot to our customer (Dixtal) 
pxa255 board.

Everything is working fine, including support to ethernet interface.

We are using bdiGDB (BDI2000) tool for writing the u-boot binary and 
debugging.

Now that everything is working with BDI plugged and u-boot transferred 
to Flash Memory 0x00000000 address. With BDI we issue "reset" and 
"go"and u-boot comes up and boots the kernel(one more "go") and linux 
root file system from flash.

When we unplugged the BDI2000 and powered-up the board u-boot did not 
come up.

We found out that with BDI2000, after reset, the PC points to  
0x00000050. If we issue go 0x00000050 the u-boot works fine and if we 
issue go 0x00000000 (as per power-up sequence) it does not work. It 
seems that the u-boot is not prepared to be booted (0x00000000 entry 
point) at power-up.

We checked the u-boot configuration file (attached below) as well as 
u-boot.lds, as far as we understand u-boot should support 0x00000000 
entry point.

Are we missing anything ? Any suggestions to solve this problem ?

Thank You,
Seido Nakanishi


==================U-boot configuration file =================
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * If we are developing, we might want to start armboot from ram
 * so we MUST NOT initialize critical regs like mem-timing ...
 */
#define CONFIG_INIT_CRITICAL        /* undef for developing */
#define DEBUG

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250        1    /* This is an PXA250 CPU    */
#define CONFIG_LUBBOCK        1    /* on an LUBBOCK Board        */
/*#define CONFIG_LCD        1
#define CONFIG_MMC        1 */
#undef CONFIG_MMC
#define BOARD_LATE_INIT        1
#define RTC            1   

#undef CONFIG_USE_IRQ            /* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN        (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE    128    /* size in bytes reserved for 
initial data */

/*
 * SMSC91C111 Network Card
 */
#define CONFIG_DRIVER_SMC91111        1
#define CONFIG_SMC91111_BASE        0x08000300 /* chip select 2         */
#undef  CONFIG_SMC_USE_32_BIT                   /* 16 bit bus access     */
#undef  CONFIG_SMC_91111_EXT_PHY           /* we use internal phy   */
#undef  CONFIG_SHOW_ACTIVITY
#define CONFIG_NET_RETRY_COUNT        10       /* # of retries          */

/*
 * select serial console configuration
 */
#define CONFIG_FFUART           1       /* we use FFUART on LUBBOCK */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE        115200

/*#define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_MMC | 
CFG_CMD_FAT) */
#define CONFIG_COMMANDS        
(CFG_CMD_BDI|CFG_CMD_LCDDRAW|CFG_CMD_LCDTST|CFG_CMD_LOADS|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_CACHE|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_BOOTD|CFG_CMD_CONSOLE|CFG_CMD_ASKENV|CFG_CMD_RUN|CFG_CMD_ECHO|CFG_CMD_REGINFO|CFG_CMD_IMMAP|CFG_CMD_DHCP|CFG_CMD_AUTOSCRIPT|CFG_CMD_ELF|CFG_CMD_MISC|CFG_CMD_SDRAM|CFG_CMD_DIAG|CFG_CMD_SAVES|CFG_CMD_PING|CFG_CMD_FAT|CFG_CMD_IMLS)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Configure Network Parameters
 */
#define CONFIG_BOOTDELAY    4
#define CONFIG_ETHADDR        00:d0:c9:60:87:aa
#define CONFIG_NETMASK        255.255.0.0
#define CONFIG_IPADDR        10.0.1.222
#define CONFIG_SERVERIP        10.0.1.200


/*
 * Configure Boot Parameters
 */
#define CONFIG_BOOTCOMMAND    "bootm 0xc00000" /* kernell address at 
Flash */
#define CONFIG_BOOTARGS        "root=/dev/mtdblock1 console=ttyS0,115200 
mem=32M rootfstype=jffs2"
#define CONFIG_CMDLINE_TAG

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE    230400        /* speed to run kgdb 
serial port */
#define CONFIG_KGDB_SER_INDEX    2        /* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER        1
#define CFG_PROMPT_HUSH_PS2    "> "

#define CFG_LONGHELP                /* undef to save memory        */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT        "uboot> "        /* Monitor Command Prompt */
#else
#define CFG_PROMPT        "uboot$ "        /* Monitor Command Prompt */
#endif
#define CFG_CBSIZE        256        /* Console I/O Buffer Size    */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer 
Size */
#define CFG_MAXARGS        16        /* max number of command args    */
#define CFG_BARGSIZE        CFG_CBSIZE    /* Boot Argument Buffer Size    */
#define CFG_DEVICE_NULLDEV    1

#define CFG_MEMTEST_START    0xa0400000    /* memtest works on    */
#define CFG_MEMTEST_END        0xa0800000    /* 4 ... 8 MB in DRAM    */

#undef    CFG_CLKS_IN_HZ        /* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR        0xa2000000    /* default kernel load address */

#define CFG_HZ            3686400        /* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED        0x161        /* set core clock to 
400/200/100 MHz */

                        /* valid baudrates */
#define CFG_BAUDRATE_TABLE    { 9600, 19200, 38400, 57600, 115200 }

#define CFG_MMC_BASE        0xF0000000

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE    (128*1024)    /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ    (4*1024)    /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ    (4*1024)    /* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CFG_DRAM_BASE        0xa0000000
#define CFG_DRAM_SIZE        0x02000000

#define CONFIG_NR_DRAM_BANKS    4       /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1        0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE    0x02000000 /* 32 MB */
#define PHYS_SDRAM_2        0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE    0x00000000 /* 0 MB */
#define PHYS_SDRAM_3        0xa8000000      /* SDRAM Bank #3             */
#define PHYS_SDRAM_3_SIZE    0x00000000      /* 0 MB                 */
#define PHYS_SDRAM_4        0xac000000      /* SDRAM Bank #4             */
#define PHYS_SDRAM_4_SIZE    0x00000000      /* 0 MB                 */

/*
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS    1        /* number of flash memory 
banks        */
#define CFG_MAX_FLASH_SECT    64        /* number of sectors in flash 
        */
#define PHYS_FLASH_1        0x00000000     /* Flash Bank #1 */
#define PHYS_FLASH_SIZE        0x01000000     /* 16 MB */
#define PHYS_FLASH_BANK_SIZE    0x01000000     /* 16 MB Banks */
#define PHYS_FLASH_SECT_SIZE    0x00040000    /* 256 KB sectors (x2)(2 
chips) */
#define CFG_MONITOR_LEN        0x00040000    /* set aside space for 
U-boot        */

/* Physical setup of Flash */
#define CFG_FLASH_BASE        PHYS_FLASH_1    /* Flash starts at the 
first bank     */
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_MONITOR_BASE    CFG_FLASH_BASE    /* where does the monitor 
live?        */

#define FPGA_REGS_BASE_PHYSICAL 0x08000000

/*
 * GPIO settings
 */
#define CFG_GPSR0_VAL        0x00000000
#define CFG_GPSR1_VAL        0x00000000
#define CFG_GPSR2_VAL        0x00000000
#define CFG_GPCR0_VAL        0x00000000
#define CFG_GPCR1_VAL        0x00000000
#define CFG_GPCR2_VAL        0x00000000
#define CFG_GPDR0_VAL        0x08108000
#define CFG_GPDR1_VAL        0x00322b82
#define CFG_GPDR2_VAL        0x0001C000
#define CFG_GAFR0_L_VAL        0x80000000
#define CFG_GAFR0_U_VAL        0x80000010
#define CFG_GAFR1_L_VAL        0x099a9550
#define CFG_GAFR1_U_VAL        0x00000a08
#define CFG_GAFR2_L_VAL        0xA0000000
#define CFG_GAFR2_U_VAL        0x00000002

#define CFG_PSSR_VAL        0x00

/*
 * Memory settings
 */
#define CFG_MSC0_VAL        0x7ff124f2
#define CFG_MSC1_VAL        0x0000b8bc
#define CFG_MSC2_VAL        0x0000ffb9
#define CFG_MDCNFG_VAL        0x00001AC9
#define CFG_MDREFR_VAL        0x0009c017
#define CFG_MDMRS_VAL        0x00220032

/*
 * PCMCIA and CF Interfaces
 */
#define CFG_MECR_VAL        0x00000000
#define CFG_MCMEM0_VAL        0x00000000
#define CFG_MCMEM1_VAL        0x00000000
#define CFG_MCATT0_VAL        0x00000000
#define CFG_MCATT1_VAL        0x00000000
#define CFG_MCIO0_VAL        0x00000000
#define CFG_MCIO1_VAL        0x00000000

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */

/* FIXME */
#define CFG_ENV_IS_IN_FLASH    1
#define CFG_ENV_ADDR        (PHYS_FLASH_1 + 0x3C000)    /* Addr of 
Environment Sector    */
#define CFG_ENV_SIZE        0x4000    /* Total Size of Environment 
Sector    */
#endif    /* __CONFIG_H */