[PATCH] Re: APIC/LAPIC hanging problems on nForce2 system.

["Prakash K. Cheemplavam" <prakashkc@gmx.de>]

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>>Well, I also think it is quite stupid to only apply the fix if
>>disconnect is enabled at boot time and don't apply it if it is not. The
>>kernel dev responsible for it is rather pedantic: Fix only when needed,

[..]
> Changing _only_ "fixup" bits seems like a reasonable compromise IMO.
> Could you (or Martin) make a patch and submit it to -mm for testing?

Ok, here it goes. It's the first time I write a patch for the kernel, so
please don't bash me. I hope my logics were alright, so please
proof-read it. I haven't tested it yet...

It simplifies the function to

static void __init pci_fixup_nforce2(struct pci_dev *dev)
{
	u32 val;

	/*
	 * Chip  Old value   New value
	 * C17   0x1F0FFF01  0x1F01FF01
	 * C18D  0x9F0FFF01  0x9F01FF01
	 *
	 * Northbridge chip version may be determined by
	 * reading the PCI revision ID (0xC1 or greater is C18D).
	 */
	pci_read_config_dword(dev, 0x6c, &val);

	/*
	 * Apply fixup if needed, but don't touch disconnect state
	 */
	if ((val & 0x00FF0000) != 0x00010000) {
		printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
	}
}



This patch applies the Nforce2 C1 halt disconnect fix, no matter if
disconnect is enabled of not. I don't know whether checking the whole
affected byte is necessary or the nibble would be enough (I am no Nvidia
engineer).

Signed-off-by: Prakash Punnoor <prakashp@arcor.de>

(My name is soon officially to be changed, in case you are wondering.)


--- arch/i386/pci/fixup.c.o	2005-01-06 15:43:40.535842320 +0100
+++ arch/i386/pci/fixup.c	2005-01-06 16:00:50.174313480 +0100
@@ -227,10 +227,7 @@
   */
  static void __init pci_fixup_nforce2(struct pci_dev *dev)
  {
-	u32 val, fixed_val;
-	u8 rev;
-
-	pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
+	u32 val;

  	/*
  	 * Chip  Old value   New value
@@ -240,17 +237,14 @@
  	 * Northbridge chip version may be determined by
  	 * reading the PCI revision ID (0xC1 or greater is C18D).
  	 */
-	fixed_val = rev < 0xC1 ? 0x1F01FF01 : 0x9F01FF01;
-
  	pci_read_config_dword(dev, 0x6c, &val);

  	/*
-	 * Apply fixup only if C1 Halt Disconnect is enabled
-	 * (bit28) because it is not supported on some boards.
+	 * Apply fixup if needed, but don't touch disconnect state
  	 */
-	if ((val & (1 << 28)) && val != fixed_val) {
+	if ((val & 0x00FF0000) != 0x00010000) {
  		printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
-		pci_write_config_dword(dev, 0x6c, fixed_val);
+		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
  	}
  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);



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--- arch/i386/pci/fixup.c.o	2005-01-06 15:43:40.535842320 +0100
+++ arch/i386/pci/fixup.c	2005-01-06 16:00:50.174313480 +0100
@@ -227,10 +227,7 @@
  */
 static void __init pci_fixup_nforce2(struct pci_dev *dev)
 {
-	u32 val, fixed_val;
-	u8 rev;
-
-	pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
+	u32 val;

 	/*
 	 * Chip  Old value   New value
@@ -240,17 +237,14 @@
 	 * Northbridge chip version may be determined by
 	 * reading the PCI revision ID (0xC1 or greater is C18D).
 	 */
-	fixed_val = rev < 0xC1 ? 0x1F01FF01 : 0x9F01FF01;
-
 	pci_read_config_dword(dev, 0x6c, &val);

 	/*
-	 * Apply fixup only if C1 Halt Disconnect is enabled
-	 * (bit28) because it is not supported on some boards.
+	 * Apply fixup if needed, but don't touch disconnect state
 	 */
-	if ((val & (1 << 28)) && val != fixed_val) {
+	if ((val & 0x00FF0000) != 0x00010000) {
 		printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
-		pci_write_config_dword(dev, 0x6c, fixed_val);
+		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
 	}
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);

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