Re: NAND fail testing

["David A. Marlin" <dmarlin@redhat.com>]

Charles:

Thank you for your reply.  Some additional information, the chips I am 
using are Renesas AG-AND (HN29V1G91T-30).  It was a note from Renesas 
that suggested this approach to permit erase/write fail testing.  I 
think this chip permits a "Random Data Input" operation that would 
permit writing a single byte, but I need to confirm this.  Since this 
does not appear to be a feature shared with other NAND/AND chips, it 
seems I may not be able to use our current driver/utilities to 
accomplish it (without modification).

Charles Manning wrote:
> I suggest you read the Toshiba NAND design guide before you try things like 
> this. Google for "toshiba nand flash applications design guide"
> 
> NAND is always written in a per-page mode, even if you only change a single 
> byte. Attempting what you propose will not only wear the single byte, but 
> will wear the whole page and block.
> 
> IMHO the best way to do testing is to emulate a device in RAM. It is 
> relatively simple to modify RAM contents and force the higher level to do its 
> test stuff. Trying to do it with a real hardware failure will take a long 
> time and is far harder to reproduce etc.

Agreed, but part of the testing is reading error status information back 
from the chips after the erase/write fail and determining if hardware 
ECC is possible.  I have not tried to emulate this device in RAM, but I 
don't think it is a viable option for me since producing and reading 
these error codes are part of the testing I need to perform.


Thanks again,

d.marlin