From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF5BAC38A2D for ; Tue, 25 Oct 2022 02:33:36 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9BF5584C47; Tue, 25 Oct 2022 04:33:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=volkov.fr Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=volkov.fr header.i=@volkov.fr header.b="EL195sjV"; dkim=pass (2048-bit key) header.d=volkov.fr header.i=@volkov.fr header.b="BYtb/Qwi"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id F12468455E; Tue, 25 Oct 2022 03:31:33 +0200 (CEST) Received: from mail.volkov.fr (sapphire.volkov.fr [3.18.100.122]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9DD16806EB for ; Tue, 25 Oct 2022 03:31:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=volkov.fr Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andrey@volkov.fr DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=volkov.fr; s=mail; t=1666661489; bh=+LvbDsMEuL1fMHIwVJN1VQgH4Yy0ZrdkyAM6LSGRg2s=; h=Date:From:Subject:To:Cc:From; b=EL195sjVr3tb8LvGIGEAGGeV4hiO//prseifeG03J+UOWUeLpGSuDIoMnsJoUFCX4 PIx5aDHsCfPCRNVRjRCiv+l6VE7kRj2d4L8g7bTx1cfCjCP1MWPKJkwf4kCFDj4T34 c7AZfLQd2M2M3Vg9g1X4SFT8DFeLKZbyZRWexKZE2diqaP3shMTzAPcrXBV0oLcGgl DvBRRUKqZt8MjODcY3TaIAjMb3zyyO/a7PrsadFiKDubqi5rWzmc9Hhr4s4GhBnvuN Eln0uL4+1pMllHKsaXEPUfXM7J4+d0EEspyAVMjgXSh2duVX/+NykgbazWcwi9kaSG BICz/YP1d9XcA== Authentication-Results: mail.volkov.fr; dmarc=none (p=none dis=none) header.from=volkov.fr DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=volkov.fr; s=mail; t=1666661488; bh=+LvbDsMEuL1fMHIwVJN1VQgH4Yy0ZrdkyAM6LSGRg2s=; h=Date:From:Subject:To:Cc:From; b=BYtb/QwiFAcKZpEAohjKyv1JDCLt1YwdozKCJQWebRVSX8sYVJmpu3A2mS8LzYl+n 7esV0AngM4COrTAM+Smhu1IdQBwQKOGLbHOU8K2Mk/tK2kNjSstvIzY8vWYljfDqO+ tvVk+AeJWinjekK7fq5R9voRcNaPDlTivq4BCYy7HOoqDwenGbjJQFLS0EbgXxjfBU mV8F0u255PbohG2DZliUJvnSg2ADIC+yPTc2oxwii9cwKOr7nXudLVQlxnWhFKkgEM U3/B8RGqDcBTu2dUZIduTtRgXjfDghtzoG6n4MvhEBKIpuvCKEH3bcHOrxcJolA41k F3ClXp/JfDTMQ== Message-ID: <4203bd12-2adb-96ca-3623-b92e7d752eae@volkov.fr> Date: Tue, 25 Oct 2022 03:31:26 +0200 MIME-Version: 1.0 From: Andrey Volkov Subject: [PATCH 1/2] mach-snapdragon/mach-ipq40xx: fix, merge and refactoring To: Ramon Fried , Robert Marko , Robert Marko , Robert Marko Cc: "u-boot@lists.denx.de" , Tom Rini Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 25 Oct 2022 04:33:15 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean SoC: qcom: Add missing Qualcomm's SOCs definitions to the arch KConfig From: Andrey VOLKOV Add APQ8016/APQ8096/QCS40X decls to the KConfig, convert SDM845 declaration to the hidden one (selected by target), and update mach-snapdragon/Makefile accordingly. Also move 'CONFIG_ARM64' choice to the new declarations, since 'Snapdragon' contains Cortex A7A members too. Signed-off-by: Andrey VOLKOV ---  arch/arm/Kconfig                              |    1 -  arch/arm/mach-snapdragon/Kconfig              |   23 +++++++++++++++++--  arch/arm/mach-snapdragon/Makefile             |   31 ++++++++++++++-----------  arch/arm/mach-snapdragon/pinctrl-snapdragon.c |    2 +-  drivers/reset/reset-qcom.c                    |    2 +-  5 files changed, 40 insertions(+), 19 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e83394052..a25b7f6d99 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1098,7 +1098,6 @@ config ARCH_RMOBILE    config ARCH_SNAPDRAGON      bool "Qualcomm Snapdragon SoCs" -    select ARM64      select DM      select DM_GPIO      select DM_SERIAL diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0927333306..83dd2c07a1 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -9,10 +9,27 @@ config SYS_MALLOC_F_LEN  config SPL_SYS_MALLOC_F_LEN      default 0x2000   +config APQ8016 +    bool +    select ARM64 +    default n + +config APQ8096 +    bool +    select ARM64 +    default n +  config SDM845 -    bool "Qualcomm Snapdragon 845 SoC" +    bool +    select ARM64 +    select LINUX_KERNEL_IMAGE_HEADER      default n + +config QCS40X +    bool +    select ARM64      select LINUX_KERNEL_IMAGE_HEADER +    default n    config LNX_KRNL_IMG_TEXT_OFFSET_BASE      default 0x80000000 @@ -23,6 +40,7 @@ choice  config TARGET_DRAGONBOARD410C      bool "96Boards Dragonboard 410C"      select BOARD_LATE_INIT +    select APQ8016      select ENABLE_ARM_SOC_BOOT0_HOOK      help        Support for 96Boards Dragonboard 410C. This board complies with @@ -37,6 +55,7 @@ config TARGET_DRAGONBOARD410C    config TARGET_DRAGONBOARD820C      bool "96Boards Dragonboard 820C" +    select APQ8096      help        Support for 96Boards Dragonboard 820C. This board complies with        96Board Open Platform Specifications. Features: @@ -71,7 +90,7 @@ config TARGET_STARQLTECHN    config TARGET_QCS404EVB      bool "Qualcomm Technologies, Inc. QCS404 EVB" -    select LINUX_KERNEL_IMAGE_HEADER +    select QCS40X      help        Support for Qualcomm Technologies, Inc. QCS404 evaluation board.        Features: diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index cbaaf23f6b..00997196ab 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,20 +2,23 @@  #  # (C) Copyright 2015 Mateusz Kulikowski   +obj-y += clock-snapdragon.o +obj-y += pinctrl-snapdragon.o +  obj-$(CONFIG_SDM845) += clock-sdm845.o  obj-$(CONFIG_SDM845) += sysmap-sdm845.o  obj-$(CONFIG_SDM845) += init_sdm845.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -obj-y += misc.o -obj-y += clock-snapdragon.o -obj-y += dram.o -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-apq8016.o -obj-y += pinctrl-apq8096.o -obj-y += pinctrl-qcs404.o -obj-y += pinctrl-sdm845.o -obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o -obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o +obj-$(CONFIG_SDM845) += pinctrl-sdm845.o + +obj-$(CONFIG_APQ8096) += clock-apq8096.o +obj-$(CONFIG_APQ8096) += sysmap-apq8096.o +obj-$(CONFIG_APQ8096) += pinctrl-apq8096.o + +obj-$(CONFIG_APQ8016) += clock-apq8016.o +obj-$(CONFIG_APQ8016) += sysmap-apq8016.o +obj-$(CONFIG_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_APQ8016) += misc.o dram.o + +obj-$(CONFIG_QCS40X) += clock-qcs404.o +obj-$(CONFIG_QCS40X) += sysmap-qcs404.o +obj-$(CONFIG_QCS40X) += pinctrl-qcs404.o diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index ab884ab6bf..4ed4ab4d4c 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -149,7 +149,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {      { }  };   -U_BOOT_DRIVER(pinctrl_snapdraon) = { +U_BOOT_DRIVER(pinctrl_snapdragon) = {      .name        = "pinctrl_msm",      .id        = UCLASS_PINCTRL,      .of_match    = msm_pinctrl_ids, diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 94315e76d5..2c61d6a6dc 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -102,7 +102,7 @@ static const struct qcom_reset_map gcc_qcom_resets[] = {  };  #endif   -#ifdef CONFIG_TARGET_QCS404EVB +#ifdef CONFIG_QCS40X  #include  static const struct qcom_reset_map gcc_qcom_resets[] = {      [GCC_GENI_IR_BCR] = { 0x0F000 },