From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3r2P9S0St7zDqB2 for ; Sun, 8 May 2016 08:54:51 +1000 (AEST) Received: by mail-wm0-x242.google.com with SMTP id e201so14515631wme.2 for ; Sat, 07 May 2016 15:54:51 -0700 (PDT) From: Christian Lamparter To: linux-usb@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: usb: dwc2: regression on MyBook Live Duo / Canyonlands since 4.3.0-rc4 Date: Sun, 08 May 2016 00:54:44 +0200 Message-ID: <4231696.iL6nGs74X8@debian64> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hello, I've been looking in getting the MyBook Live Duo's USB OTG port to function. The SoC is a APM82181. Which has a PowerPC 464 core and related to the supported canyonlands architecture in arch/powerpc/.= Currently in -next the dwc2 module doesn't load:=20 dwc2 4bff80000.usbotg: dwc2_core_reset() HANG! AHB Idle GRSTCTL=3D80 dwc2 4bff80000.usbotg: Bad value for GSNPSID: 0x0a29544f Looking at the Bad GSNPSID value: 0x0a29544f. It is obvious that this is an endian problem. git finds this patch: commit 95c8bc3609440af5e4a4f760b8680caea7424396 Author: Antti Sepp=E4l=E4 Date: Thu Aug 20 21:41:07 2015 +0300 usb: dwc2: Use platform endianness when accessing registers This patch is necessary to access dwc2 registers correctly on big-e= ndian systems such as the mips based SoCs made by Lantiq. Then dwc2 can b= e used to replace ifx-hcd driver for Lantiq platforms found e.g. in OpenWrt. =20 The patch was autogenerated with the following commands: $EDITOR core.h sed -i "s/\/dwc2_readl/g" *.c hcd.h hw.h sed -i "s/\/dwc2_writel/g" *.c hcd.h hw.h =20 Some files were then hand-edited to fix checkpatch.pl warnings abou= t too long lines. which unfortunately, broke the USB-OTG port on the MyBook Live Duo. Reverting to the readl / writel: ---=20 diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 3c58d63..c021c1f 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -66,7 +66,7 @@ =20 static inline u32 dwc2_readl(const void __iomem *addr) { -=09u32 value =3D __raw_readl(addr); +=09u32 value =3D readl(addr); =20 =09/* In order to preserve endianness __raw_* operation is used. There= fore =09 * a barrier is needed to ensure IO access is not re-ordered across= @@ -78,7 +78,7 @@ static inline u32 dwc2_readl(const void __iomem *addr= ) =20 static inline void dwc2_writel(u32 value, void __iomem *addr) { -=09__raw_writel(value, addr); +=09writel(value, addr); =20 =09/* =09 * In order to preserve endianness __raw_* operation is used. There= fore --- restores the dwc-otg port to full working order: dwc2 4bff80000.usbotg: Specified GNPTXFDEP=3D1024 > 256 dwc2 4bff80000.usbotg: EPs: 3, shared fifos, 2042 entries in SPRAM dwc2 4bff80000.usbotg: DWC OTG Controller dwc2 4bff80000.usbotg: new USB bus registered, assigned bus number 1 dwc2 4bff80000.usbotg: irq 33, io mem 0x00000000 hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected root@mbl:~# usb 1-1: new high-speed USB device number 2 using dwc2 So, what to do? Regards, Christian