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From: Steven Singer <steven.singer@csr.com>
To: bluez-users@lists.sourceforge.net
Subject: Re: [Bluez-users] Has anyone seen these problems with the CSR BlueCore and BlueZ before ?
Date: Thu, 17 Mar 2005 17:50:35 +0000	[thread overview]
Message-ID: <4239C36B.1090203@csr.com> (raw)
In-Reply-To: <1111078208.9741.2.camel@pegasus>

Marcel Holtmann wrote:
> Steven Singer wrote:
>> would it be a good idea to add reading of the panic and
>> fault codes to the CSR specific section of hcitool revision? Or,
>> get BlueZ to read the panic code when the inerface is brought up. If
>> it's non-zero and < 0x0100 write it to an event log and then zero it.
> 
> the kernel code should be complete vendor independent and thus adding
> this to "hciconfig hci0 revsion" is the only option.

That's OK. At least it will make it easy for users to find out this
information.

> Are both variables UINT16? If yes, then it will be quite easy to add
> this information to the hciconfig command.

Yes.

>                                            What document should I read
> for more information about the panic/fault code meanings?

HQ Commands (bcore-sp-003Pc). They're in section 6.

In addition to the information in there, you can decode the following:

  0x0080-0x00ff: Debugging codes. These should be used only within CSR
                 for testing purposes and, in theory, should not make it
                 into released code, but you never know.

  0x0100-0xffff: No panic/fault since last power cycle. When the chip is
                 powered on, the panic and fault codes usually end up
                 somewhere in this area. In theory they could end up in
                 the valid range, but it's unlikely. We don't use codes
                 in this area for real panics or faults.

If you want to test them, then the BCCMD variables are writable so you
should be able to write to them, read them back, and confirm that
they're preserved across reset but not power cycle.

If you want to test them further, then writing to variables 0x4820 and
0x4822 will cause the chip to panic or fault respectively. Each takes a
single 16 bit argument containg the code to use. In the case of panic,
this means that the chip will reset (unless the watchdog is disabled).
In the case of fault, an HCI Hardware_Error event and an HQ PDU should
be emitted.

If you're writing the codes or provoking the actions via BCCMD then you
can specify codes outside the normally valid range. This means you
should be able to test the full range your decode.

	- Steven
-- 


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  reply	other threads:[~2005-03-17 17:50 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-03-17 13:30 [Bluez-users] Has anyone seen these problems with the CSR BlueCore and BlueZ before ? Han Hoekstra
2005-03-17 14:02 ` Marcel Holtmann
2005-03-17 14:19   ` [Bluez-users] Has anyone seen these problems with the CSRBlueCore " Han Hoekstra
2005-03-17 14:58     ` Marcel Holtmann
2005-03-17 15:43       ` [Bluez-users] Has anyone seen these problems with theCSRBlueCore " Han Hoekstra
2005-03-17 15:35 ` [Bluez-users] Has anyone seen these problems with the CSR BlueCore " Erwin Authried
2005-03-17 16:28 ` Steven Singer
2005-03-17 16:50   ` Marcel Holtmann
2005-03-17 17:50     ` Steven Singer [this message]
2005-03-17 19:06       ` Marcel Holtmann

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