From: Jeff Garzik <jgarzik@pobox.com>
To: Michael Chan <mchan@broadcom.com>
Cc: "David S. Miller" <davem@davemloft.net>, netdev@oss.sgi.com
Subject: Re: [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt
Date: Tue, 22 Mar 2005 15:53:29 -0500 [thread overview]
Message-ID: <424085C9.3020608@pobox.com> (raw)
In-Reply-To: <B1508D50A0692F42B217C22C02D84972020F3E22@NT-IRVA-0741.brcm.ad.broadcom.com>
Michael Chan wrote:
> Add register read of PCI state register in tg3_interrupt() if status block's
> updated bit is not set. This will flush the status block and confirm whether
> the interrupt is ours or not. PCI ordering rules allow the interrupt to
> arrive at the CPU ahead of the status block that may be posted at the
> chipset.
>
> Signed-off-by: Michael Chan <mchan@broadcom.com
ACK
next prev parent reply other threads:[~2005-03-22 20:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-03-21 7:26 [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt Michael Chan
2005-03-22 20:53 ` Jeff Garzik [this message]
2005-03-23 19:07 ` David S. Miller
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