[Qemu-devel] Re: request : qemu-smp as target

[Fabrice Bellard <fabrice@bellard.org>]

Blue Swirl wrote:
> Hi,
> 
> The architecture used in sparc target (sun4m) supports SMP up to a 
> maximum of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), 
> it would be easy to add the missing interprocessor interrupts, per-CPU 
> counters and atomic instructions. It would also be simple to add the 
> prom functions for starting/stopping CPUs to Proll. Maybe some days' 
> work in total.
> 
> Higher level (vl.c, cpu-exec.c) could need more work. Maybe Fabrice can 
> enlighten us?

SMP est definitely possible in QEMU - a few days of work are necessary 
to add the missing generic support and an x86 implementation... but 
currently I prefer to work an other topics.

Just for your information, some choices need to be made:

1) Do the CPUs share the same translation cache ?

2) The first implementation would use a cycle counter to schedule 
between CPUs. Is it interesting to go further and to use a host thread 
for each guest CPU at the expense of more locking overhead ?

Fabrice.