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Sun, 29 May 2022 21:44:39 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Sun, 29 May 2022 21:44:39 -0700 Received: from fmsmsx610.amr.corp.intel.com ([10.18.126.90]) by fmsmsx610.amr.corp.intel.com ([10.18.126.90]) with mapi id 15.01.2308.027; Sun, 29 May 2022 21:44:39 -0700 From: "Gupta, Anshuman" To: "Nikula, Jani" , "intel-gfx@lists.freedesktop.org" , "Roper, Matthew D" Thread-Topic: [PATCH 3/7] drm/i915/dg2: DG2 MBD config Thread-Index: AQHYarg/c9jrXjH9c0+i2Od1sFFkU60mZRAAgBCC4yA= Date: Mon, 30 May 2022 04:44:38 +0000 Message-ID: <4299ea60a4c74ea0806d78b09de0b6c6@intel.com> References: <20220518130716.10936-1-anshuman.gupta@intel.com> <20220518130716.10936-4-anshuman.gupta@intel.com> <87h75ldg9t.fsf@intel.com> In-Reply-To: <87h75ldg9t.fsf@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.6.500.17 dlp-reaction: no-action x-originating-ip: [10.223.10.1] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915/dg2: DG2 MBD config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Vivi, Rodrigo" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Nikula, Jani > Sent: Thursday, May 19, 2022 2:57 PM > To: Gupta, Anshuman ; intel- > gfx@lists.freedesktop.org > Cc: Nilawar, Badal ; Ewins, Jon > ; Vivi, Rodrigo ; Deak, Imre > ; Gupta, Anshuman > Subject: Re: [PATCH 3/7] drm/i915/dg2: DG2 MBD config >=20 > On Wed, 18 May 2022, Anshuman Gupta wrote: > > Add DG2 Motherboard Down Config check support. > > > > BSpec: 44477 > > Cc: Rodrigo Vivi > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++ > > drivers/gpu/drm/i915/i915_drv.h | 9 +++++++++ > > 2 files changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c > > b/drivers/gpu/drm/i915/display/intel_opregion.c > > index 3dcd54517b89..dec7628522c5 100644 > > --- a/drivers/gpu/drm/i915/display/intel_opregion.c > > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c > > @@ -1271,6 +1271,8 @@ intel_opregion_vram_sr_required(struct > > drm_i915_private *i915) > > > > if (IS_DG1(i915)) > > return intel_opregion_dg1_mbd_config(i915); > > + else if (IS_DG2_MBD(i915)) > > + return true; > > > > return false; > > } > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > b/drivers/gpu/drm/i915/i915_drv.h index 10f273800645..c5ecc490dced > > 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1071,6 +1071,15 @@ IS_SUBPLATFORM(const struct drm_i915_private > *i915, > > IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) > #define > > IS_DG2_G12(dev_priv) \ > > IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) > > +/* > > + * FIXME: Need to define a new SUBPLATFORM > INTEL_SUBPLATFORM_DG2_MBD > > + * for PCI id range 5690..5695, but G10, G11 SUBPLATFROM conflicts > > + * with those pci id range. > > + */ > > +#define DG2_MBD_CONFIG_MASK GENMASK(7, 4) > > +#define DG2_MBD_CONFIG_VAL > FIELD_PREP(DG2_MBD_CONFIG_MASK, 9) > > +#define IS_DG2_MBD(dev_priv) (IS_DG2(dev_priv) && \ > > + (INTEL_DEVID(dev_priv) & > DG2_MBD_CONFIG_MASK) =3D=3D > > +DG2_MBD_CONFIG_VAL) >=20 > No. Please don't do *any* magic masking or comparison of PCI ID bits or > bitfields. Hi Matt, We need to distinguish between DG2 NB MBD and rest such that i915 can figur= e out opregion vram_sr is requires for the DG2 platform. Could you please = suggestion on that. Thanks, Anshuman Gupta. >=20 > BR, > Jani. >=20 > > #define IS_ADLS_RPLS(dev_priv) \ > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, > INTEL_SUBPLATFORM_RPL) > > #define IS_ADLP_N(dev_priv) \ >=20 > -- > Jani Nikula, Intel Open Source Graphics Center