From: Jeff Garzik <jgarzik@pobox.com>
To: "David S. Miller" <davem@davemloft.net>,
raghavendra.koushik@neterion.com
Cc: akepner@sgi.com, netdev@oss.sgi.com, netdev@vger.kernel.org,
ravinandan.arakali@neterion.com, leonid.grossman@neterion.com,
rapuru.sriram@neterion.com
Subject: Re: [PATCH 2.6.12.1 5/12] S2io: Performance improvements
Date: Thu, 07 Jul 2005 23:08:02 -0400 [thread overview]
Message-ID: <42CDEE12.5030100@pobox.com> (raw)
In-Reply-To: <20050707.200034.74747399.davem@davemloft.net>
David S. Miller wrote:
> If you need a PIO to complete in a specific order, you
> have to read it back. If you need PIO operations to occur
Correct.
A PCI read is the only way to ensure that all the CPU/PCI bridge buffers
are flushed to the device.
Whenever Arjan and I complain about "PCI posting" problems, we are
indicating a need for additional readl() calls to ensure
ordering/flushing. Delaying immediately after a writel() is a classic
PCI posting mistake. Assuming ordering is another.
Jeff
next prev parent reply other threads:[~2005-07-08 3:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-07-07 22:27 [PATCH 2.6.12.1 5/12] S2io: Performance improvements raghavendra.koushik
2005-07-07 23:15 ` Arthur Kepner
2005-07-08 1:06 ` Raghavendra Koushik
2005-07-08 3:00 ` David S. Miller
2005-07-08 3:08 ` Jeff Garzik [this message]
2005-07-08 15:31 ` Arthur Kepner
2005-07-08 18:16 ` Raghavendra Koushik
2005-07-08 18:17 ` Ravinandan Arakali
2005-07-12 20:27 ` Christoph Hellwig
2005-07-12 20:34 ` David S. Miller
2005-07-12 21:00 ` Ravinandan Arakali
2005-07-12 21:04 ` David S. Miller
2005-07-12 21:07 ` Christoph Hellwig
2005-07-12 21:26 ` Andi Kleen
2005-07-12 21:54 ` Ravinandan Arakali
2005-07-29 16:37 ` Ravinandan Arakali
2005-07-31 14:05 ` Christoph Hellwig
2005-08-02 23:13 ` Ravinandan Arakali
2005-08-02 23:26 ` 'Christoph Hellwig'
2005-07-12 20:56 ` Leonid Grossman
-- strict thread matches above, loose matches on Subject: below --
2005-08-03 12:48 Prarit Bhargava
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