Filip Navara wrote:
[snip]

> qemu-20050718-02-insns.patch
>        - Add support for AMD cache info MCR.
>        - Fix INVLPG instruction in 64bit mode.
>        - Implement the ENTER instruction for 64bit mode.
>        - Add dummy support for MCA, PAT, MTRR and CLFLUSH.
>        - Correct size of 16bit stack pushes in 64bit mode.
>        - Correct segment arithmetics for various instructions in 64bit 
> mode.
>        - Correctly honour the ADDR prefix for these instrutions:
>          maskmov; mov EAX, Ov; mov Ov, EAX
>        - Fix the implicit 64bit semantics for these instrutions:
>          ret im; lcall; lret
>        - Support the PREFETCHW instruction.

This time with the correct patch (qemu-20050721-02-insns.patch).

> qemu-20050718-03-apic.patch 

[snip]
I forgot to credit malc_ for his extensive testing, ideas and general 
help with this patch. Thanks!

- Filip