From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.dev.rtsoft.ru (RT-soft-2.Moscow.itn.ru [80.240.96.70]) by ozlabs.org (Postfix) with SMTP id 2E57B67EAD for ; Thu, 4 Aug 2005 00:36:00 +1000 (EST) Message-ID: <42F0D64F.80600@ru.mvista.com> Date: Wed, 03 Aug 2005 18:35:59 +0400 From: Vitaly Bordug MIME-Version: 1.0 To: "Schaefer-Hutter, Peter" References: <8E342283C2100540AAC5D103097054776F8533@rcexc.racoms.loc> In-Reply-To: <8E342283C2100540AAC5D103097054776F8533@rcexc.racoms.loc> Content-Type: multipart/alternative; boundary="------------010904070501010007050402" Cc: linuxppc-embedded list Subject: Re: MPC885ADS and 2.6.13-rc5 - nogo ? List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. --------------010904070501010007050402 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Schaefer-Hutter, Peter wrote: >Hello, > > > >>From: Vitaly Bordug [mailto:vbordug@ru.mvista.com] >> >> > > > >>The board does not hang - there's somithing with >>console since you don't see anything. Try to change >>BCSR_ADDR from 0xf4500000 to 0xf80...0 - the newer >>version of the boards may have this changed. >> >> > >Hrm... arc/ppc/mpc885ads.h already reads > > /* U-Boot maps BCSR to 0xff080000 */ > #define BCSR_ADDR ((uint)0xff080000) > >And that's the same setting that my 2.4-Kernel >uses, so it should work with 0xff080000. > >However, BCSR_SIZE looks suspicious in this header: > > #define BCSR_SIZE ((uint)32) > >Shouldn't that read: > > #define BCSR_SIZE ((uint)32 * 1024) > >??!? > >Regards, > > Peter > > > (This is from 8272 User Guide, but 885 I guess is the same in this part) > Most of the hardware options on the MPC8272ADS are controlled or > monitored by the > BCSR, which is a 32 bit wide read / write register file. The BCSR is > accessed via the > MPC8272s' memory controller (see Table 5-5) and in fact includes 8 > registers: BCSR0 to > BCSR7. Since the minimum block size for a CS region is 32KBytes and > only A(27:29) > lines are decoded by the BCSR for register selection, BCSR0 - BCSR7 > are duplicated inside > that region. -- Sincerely, Vitaly --------------010904070501010007050402 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Schaefer-Hutter, Peter wrote: 
Hello,

  
From: Vitaly Bordug [mailto:vbordug@ru.mvista.com] 
    

  
The board does not hang - there's somithing with 
console since you don't see anything.  Try to change 
BCSR_ADDR from 0xf4500000 to 0xf80...0 - the newer 
version of the boards may have this changed.
    

Hrm... arc/ppc/mpc885ads.h already reads

  /* U-Boot maps BCSR to 0xff080000 */
  #define BCSR_ADDR   ((uint)0xff080000)

And that's the same setting that my 2.4-Kernel
uses, so it should work with 0xff080000.

However, BCSR_SIZE looks suspicious in this header:

  #define BCSR_SIZE   ((uint)32)

Shouldn't that read:

  #define BCSR_SIZE   ((uint)32 * 1024)

??!?

Regards,

  Peter
<quotation> (This is from 8272 User Guide, but 885 I guess is the same in this part)
Most of the hardware options on the MPC8272ADS are controlled or monitored by the
BCSR, which is a 32 bit wide read / write register file. The BCSR is accessed via the
MPC8272s’ memory controller (see Table 5-5) and in fact includes 8 registers: BCSR0 to
BCSR7. Since the minimum block size for a CS region is 32KBytes and only A(27:29)
lines are decoded by the BCSR for register selection, BCSR0 - BCSR7 are duplicated inside
that region.
<quotation\>

-- 
Sincerely, 
Vitaly
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