Re: [PATCH] transition latency of speedstep-ich (third try)

[Eric Piel <Eric.Piel@tremplin-utc.net>]

29.09.2005 01:53, Pallipadi, Venkatesh wrote/a écrit:
>>-----Original Message-----
>>From: Eric Piel [mailto:Eric.Piel@tremplin-utc.net] 
>>
>>>Eric,
>>>Can you put rdtsc's around these in/out on your system and 
>>
>>check how long do they really take. On P4M, rdtsc should be 
>>running all the time other than the Cpu being in deep_sleep 
>>state. That should give us some idea about the SMM latency.
>>
>>Ok, I've just done it. It's on a P3 coppermine though (not a P4M). So 
>>I've measure the difference of tsc before and after the in/out 
>>instructions (not included the local_irq_*()). The patch is 
>>attached for 
>>double check (or if someone wants to try on another CPU). The values 
>>seem very small compare to the 500uS you mentioned.
>>
>>After few minutes with ondemand governor, there was a log like this:
>>Sep 28 23:30:32 circle kernel: cpufreq transition took 4862 cycles
>>Sep 28 23:30:33 circle kernel: cpufreq transition took 4473 cycles
>>Sep 28 23:30:33 circle kernel: cpufreq transition took 4836 cycles
>>Sep 28 23:30:35 circle kernel: cpufreq transition took 4723 cycles
>>Sep 28 23:30:35 circle kernel: cpufreq transition took 5640 cycles
>>Sep 28 23:30:48 circle kernel: cpufreq transition took 4515 cycles
>>Sep 28 23:30:48 circle kernel: cpufreq transition took 4904 cycles
>>Sep 28 23:31:02 circle kernel: cpufreq transition took 4286 cycles
>>Sep 28 23:31:02 circle kernel: cpufreq transition took 4607 cycles
>>Sep 28 23:31:03 circle kernel: cpufreq transition took 4279 cycles
>>Sep 28 23:31:03 circle kernel: cpufreq transition took 4605 cycles
>>Sep 28 23:31:04 circle kernel: cpufreq transition took 4694 cycles
>>Sep 28 23:31:04 circle kernel: cpufreq transition took 4605 cycles
>>Sep 28 23:31:13 circle kernel: cpufreq transition took 4683 cycles
>>Sep 28 23:31:14 circle kernel: cpufreq transition took 4676 cycles
>>Sep 28 23:31:14 circle kernel: cpufreq transition took 4515 cycles
>>Sep 28 23:31:15 circle kernel: cpufreq transition took 4522 cycles
>>
>>Maximum I've seen is 5640 cycles, minimum is about 4200c. My CPU is 
>>clocked 1GHz so the result can be easily summarized to a maximum of 
>>about 6uS.
>>
>>As it's very different from the numbers you got, I wonder if I mistook 
>>somewhere ?
>>
> 
> 
> I don't have any numbers with Coppermine or P4-M. Probably the reason
> For low numbers is TSC itself stops at certain times during this whole
> Operation. And it will also run at slower frequency once you change the
> Freq (On coppermine). 6uS is too low in my opinion. We may not be 
> measuring correctly here.
Could it happen that on a P4M the TSC doesn't stop? Then maybe someone 
with such a harware could try? Otherwise, what do you suggest to obtain 
the maximum transition latency? Take 500uS and multiply by the number of 
I/O in the code ?

Eric