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From: Suresh Chandra Mannava <msuresh@gamebox.net>
To: linuxppc-embedded@ozlabs.org
Subject: SMP Design
Date: Fri, 28 Oct 2005 12:30:11 +0530	[thread overview]
Message-ID: <4361CC7B.7080304@gamebox.net> (raw)

Hi,
I am working on a symmetric multiprocessing(SMP) based board design.  
Now,  I am into feasibility analysis.
Here are my queries
What qualifies a CPU to be capable of SMP?
       Hardware cache coherency
       test-and-set, compare-and-swap or load-link/ store-conditional 
instructions.
       Unique Id(read this in Intel MP specs) Is it required for 
powerpc-smp?
       CPU-local interrupt controller (intel specific) Is it required 
for powerpc-smp
       OpenPIC, interrupt routing
 
what are the other points that support SMP for a CPU. I read that ppc 
603 won't support pure SMP.

I am searching for the "considerations for SMP design using powerpc 
processors"
please provide pointers for the same.

Can I find any reference design for SMP boards? I am interested 
architecture part, interrupt routing and OpenPIC stuff.
I find it hard to find information on SMP board design.

Waiting for your response.

Thanks and Regards,
Suresh Chandra Mannava.

                 reply	other threads:[~2005-10-28  7:42 UTC|newest]

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