Re: MIPS - 64bit woes

[Jim Gifford <maillist@jg555.com>]

Ok,
    Isolated the problem down to one file, will see if this patch will 
fix the issue with 2.6.14, the patch is the a diff of a file from 
2.6.13-rc2 and 2.6.13-rc3 which introduced the issue. Here is a link to 
the patch http://ftp.jg555.com/cobalt/culprit

Will test 2.6.14 with this patch a report back.

diff -Naur linux-mips-2.6.13-rc3/arch/mips/kernel/cpu-probe.c 
testbed/arch/mips/kernel/cpu-probe.c
--- linux-mips-2.6.13-rc3/arch/mips/kernel/cpu-probe.c    2005-07-27 
14:48:12.000000000 -0700
+++ testbed/arch/mips/kernel/cpu-probe.c    2005-11-17 
14:18:56.000000000 -0800
@@ -71,27 +71,11 @@
         : : "r" (au1k_wait));
 }
 
-static int __initdata nowait = 0;
-
-int __init wait_disable(char *s)
-{
-    nowait = 1;
-
-    return 1;
-}
-
-__setup("nowait", wait_disable);
-
 static inline void check_wait(void)
 {
     struct cpuinfo_mips *c = &current_cpu_data;
 
     printk("Checking for 'wait' instruction... ");
-    if (nowait) {
-        printk (" disabled.\n");
-        return;
-    }
-
     switch (c->cputype) {
     case CPU_R3081:
     case CPU_R3081E:
@@ -121,7 +105,6 @@
     case CPU_24K:
     case CPU_25KF:
     case CPU_34K:
-     case CPU_PR4450:
         cpu_wait = r4k_wait;
         printk(" available.\n");
         break;
@@ -147,6 +130,58 @@
     check_wait();
 }
 
+#ifdef CONFIG_64BIT
+
+/*
+ * On RM5230/5231 all accesses to XKPHYS by LL(D) are forced
+ * to be uncached, bits 61-59 of the address are ignored.
+ *
+ * Apparently fixed on RM5230A/5231A.
+ */
+static inline int check_lld(void)
+{
+    unsigned long flags, value, match, phys, *addr;
+
+    printk("Checking for lld bug... ");
+
+    /* hope the stack is in the low 512MB */
+    phys = CPHYSADDR((unsigned long) &value);
+
+    /* write value to memory */
+    value = 0xfedcba9876543210;
+    addr = (unsigned long *) PHYS_TO_XKPHYS(K_CALG_UNCACHED, phys);
+    *addr = value;
+
+    /* stop spurious flushes */
+    local_irq_save(flags);
+
+    /* flip cached value */
+    value = ~value;
+
+    /* read value, supposedly from cache */
+    addr = (unsigned long *) PHYS_TO_XKPHYS(K_CALG_NONCOHERENT, phys);
+    asm volatile("lld %0, %1" : "=r" (match) : "m" (*addr));
+
+    local_irq_restore(flags);
+
+    match ^= value;
+
+    switch ((long) match) {
+    case 0:
+        printk("no.\n");
+        break;
+    case -1:
+        printk("yes.\n");
+        break;
+    default:
+        printk("yikes yes! (%lx/%lx@%p)\nPlease report to 
<linux-mips@linux-mips.org>.", value, match, &value);
+    }
+
+    return !match;
+}
+
+#endif
+
 /*
  * Probe whether cpu has config register by trying to play with
  * alternate cache bit and see whether it matters.
@@ -283,8 +318,7 @@
     case PRID_IMP_R4600:
         c->cputype = CPU_R4600;
         c->isa_level = MIPS_CPU_ISA_III;
-        c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
-                 MIPS_CPU_LLSC;
+        c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
         c->tlbsize = 48;
         break;
     #if 0
@@ -364,7 +398,11 @@
         c->cputype = CPU_NEVADA;
         c->isa_level = MIPS_CPU_ISA_IV;
         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
-                     MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
+                     MIPS_CPU_DIVEC;
+#ifdef CONFIG_64BIT
+        if (check_lld())
+#endif
+            c->options |= MIPS_CPU_LLSC;
         c->tlbsize = 48;
         break;
     case PRID_IMP_R6000:
@@ -509,12 +547,6 @@
         c->ases |= MIPS_ASE_SMARTMIPS;
     if (config3 & MIPS_CONF3_DSP)
         c->ases |= MIPS_ASE_DSP;
-    if (config3 & MIPS_CONF3_VINT)
-        c->ases |= MIPS_CPU_VINT;
-    if (config3 & MIPS_CONF3_VEIC)
-        c->ases |= MIPS_CPU_VEIC;
-    if (config3 & MIPS_CONF3_MT)
-                c->ases |= MIPS_CPU_MIPSMT;
 
     return config3 & MIPS_CONF_M;
 }
@@ -632,21 +664,6 @@
     }
 }
 
-static inline void cpu_probe_philips(struct cpuinfo_mips *c)
-{
-    decode_configs(c);
-    switch (c->processor_id & 0xff00) {
-    case PRID_IMP_PR4450:
-        c->cputype = CPU_PR4450;
-        c->isa_level = MIPS_CPU_ISA_M32;
-        break;
-    default:
-        panic("Unknown Philips Core!"); /* REVISIT: die? */
-        break;
-    }
-}
-
-
 __init void cpu_probe(void)
 {
     struct cpuinfo_mips *c = &current_cpu_data;
@@ -672,9 +689,6 @@
     case PRID_COMP_SANDCRAFT:
         cpu_probe_sandcraft(c);
         break;
-     case PRID_COMP_PHILIPS:
-        cpu_probe_philips(c);
-         break;
     default:
         c->cputype = CPU_UNKNOWN;
     }

-- 
----
Jim Gifford
maillist@jg555.com